From 7c031e230182944c53a77c422c84793153a420f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jul 2020 11:59:52 +0100 Subject: [PATCH] remove FHDLTestCase --- src/soc/fu/cr/test/test_pipe_caller.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 4c389d34..904fc5e7 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -1,6 +1,5 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import ISACaller, special_sprs @@ -180,7 +179,7 @@ def get_cu_inputs(dec2, sim): return res -class TestRunner(FHDLTestCase): +class TestRunner(unittest.TestCase): def __init__(self, test_data): super().__init__("run_all") self.test_data = test_data -- 2.30.2