From 7c1b9388caa27c1f4f1c296ddf4ff26bd394f340 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 24 Jul 2019 22:47:32 +0100 Subject: [PATCH] add TLB elaboratable --- src/TLB/ariane/tlb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/TLB/ariane/tlb.py b/src/TLB/ariane/tlb.py index 1f1fa86c..6a29cf61 100644 --- a/src/TLB/ariane/tlb.py +++ b/src/TLB/ariane/tlb.py @@ -25,7 +25,7 @@ Online simulator: http://www.ntu.edu.sg/home/smitha/ParaCache/Paracache/vm.html """ from math import log2 -from nmigen import Signal, Module, Cat, Const, Array +from nmigen import Signal, Module, Cat, Const, Array, Elaboratable from nmigen.cli import verilog, rtlil from nmigen.lib.coding import Encoder @@ -35,7 +35,7 @@ from TLB.ariane.tlb_content import TLBContent TLB_ENTRIES = 8 -class TLB: +class TLB(Elaboratable): def __init__(self, tlb_entries=8, asid_width=8): self.tlb_entries = tlb_entries self.asid_width = asid_width -- 2.30.2