From 7c26a9396964550850b507c7031a1aac5d3228f8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Sep 2021 22:01:58 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 8137c0070..86fa66908 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -100,9 +100,10 @@ to enact them each based on whether testing succeeds *or fails*. This results in a not-insignificant number of additional Mode Augmentation bits, accompanying VLSET and CTR-test Modes respectively. -It is also important to note that Vectorised Branches can be used -in either SVP64 Horizontal-First or Vertical-First Mode. Essentially -the behaviour is identical in both Modes. +Vectorised Branches can be used +in either SVP64 Horizontal-First or Vertical-First Mode. Essentially, +at an element level, the behaviour is identical in both Modes, +although the `ALL` bit is meaningless in Vertical-First Mode. It is also important to bear in mind that, fundamentally, Vectorised Branch-Conditional -- 2.30.2