From 7c42a3675c791b2eafae4a352a7d8adbe510e027 Mon Sep 17 00:00:00 2001 From: James Bowman Date: Thu, 2 Nov 2017 19:41:02 +0000 Subject: [PATCH] Add FT32B support FT32B is a new FT32 architecture type. FT32B has a code compression scheme which uses linker relaxations. It also has a security option to prevent reads from program memory. gcc/ * config/ft32/ft32.c (ft32_addr_space_legitimate_address_p): increase offset range for FT32B. * config/ft32/ft32.h: option "mcompress" enables relaxation. * config/ft32/ft32.md: Add TARGET_NOPM. * config/ft32/ft32.opt: Add mft32b, mcompress, mnopm. * gcc/doc/invoke.texi: Add mft32b, mcompress, mnopm. From-SVN: r254351 --- gcc/ChangeLog | 9 +++++++++ gcc/config/ft32/ft32.c | 7 +++++-- gcc/config/ft32/ft32.h | 7 ++++--- gcc/config/ft32/ft32.md | 8 ++++++-- gcc/config/ft32/ft32.opt | 12 ++++++++++++ gcc/doc/invoke.texi | 14 +++++++++++++- 6 files changed, 49 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0af62d17265..574793efe79 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-11-02 James Bowman + + * config/ft32/ft32.c (ft32_addr_space_legitimate_address_p): increase + offset range for FT32B. + * config/ft32/ft32.h: option "mcompress" enables relaxation. + * config/ft32/ft32.md: Add TARGET_NOPM. + * config/ft32/ft32.opt: Add mft32b, mcompress, mnopm. + * gcc/doc/invoke.texi: Add mft32b, mcompress, mnopm. + 2017-11-02 Wilco Dijkstra * config/aarch64/aarch64.h (MALLOC_ABI_ALIGNMENT): New define. diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c index 0386e068f3b..d7d41a2f3ca 100644 --- a/gcc/config/ft32/ft32.c +++ b/gcc/config/ft32/ft32.c @@ -866,6 +866,8 @@ static bool ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, addr_space_t as ATTRIBUTE_UNUSED) { + int max_offset = TARGET_FT32B ? 16384 : 128; + if (mode != BLKmode) { if (GET_CODE (x) == PLUS) @@ -875,8 +877,9 @@ ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, op2 = XEXP (x, 1); if (GET_CODE (op1) == REG && CONST_INT_P (op2) - && INTVAL (op2) >= -128 - && INTVAL (op2) < 128 && reg_ok_for_base_p (op1, strict)) + && (-max_offset <= INTVAL (op2)) + && (INTVAL (op2) < max_offset) + && reg_ok_for_base_p (op1, strict)) goto yes; if (GET_CODE (op1) == SYMBOL_REF && CONST_INT_P (op2)) goto yes; diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h index d52bb9af17c..8bb0d399a0c 100644 --- a/gcc/config/ft32/ft32.h +++ b/gcc/config/ft32/ft32.h @@ -39,6 +39,7 @@ #undef LIB_SPEC #define LIB_SPEC "%{!shared:%{!symbolic:-lc}} \ + %{mcompress:--relax} \ %{msim:-Tsim.ld}" #undef LINK_SPEC @@ -199,12 +200,12 @@ enum reg_class #define GLOBAL_ASM_OP "\t.global\t" -#define JUMP_TABLES_IN_TEXT_SECTION 1 +#define JUMP_TABLES_IN_TEXT_SECTION (TARGET_NOPM ? 0 : 1) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\tjmp\t.L%d\n", VALUE); \ + fprintf (FILE, "\t.long\t.L%d\n", VALUE); \ /* Passing Arguments in Registers */ @@ -469,7 +470,7 @@ do { \ #define ADDR_SPACE_PM 1 #define REGISTER_TARGET_PRAGMAS() do { \ - c_register_addr_space ("__flash__", ADDR_SPACE_PM); \ + c_register_addr_space ("__flash__", TARGET_NOPM ? 0 : ADDR_SPACE_PM); \ } while (0); extern int ft32_is_mem_pm(rtx o); diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md index 984c3b67e32..2e772faf72f 100644 --- a/gcc/config/ft32/ft32.md +++ b/gcc/config/ft32/ft32.md @@ -777,8 +777,12 @@ (clobber (match_scratch:SI 2 "=&r")) ] "" - "ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;jmpi\t%2" - ) + { + if (TARGET_NOPM) + return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;ldi.l\t%2,%2,0\;jmpi\t%2\"; + else + return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;lpmi.l\t%2,%2,0\;jmpi\t%2\"; + }) ;; ------------------------------------------------------------------------- ;; Atomic exchange instruction diff --git a/gcc/config/ft32/ft32.opt b/gcc/config/ft32/ft32.opt index ba01c81ecf1..9e75f340335 100644 --- a/gcc/config/ft32/ft32.opt +++ b/gcc/config/ft32/ft32.opt @@ -29,3 +29,15 @@ Use LRA instead of reload. mnodiv Target Report Mask(NODIV) Avoid use of the DIV and MOD instructions + +mft32b +Target Report Mask(FT32B) +target the FT32B architecture + +mcompress +Target Report Mask(COMPRESS) +enable FT32B code compression + +mnopm +Target Report Mask(NOPM) +Avoid placing any readable data in program memory diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1533a129c25..e47a0e32b77 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -743,7 +743,7 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-msmall-model -mno-lsim} @emph{FT32 Options} -@gccoptlist{-msim -mlra -mnodiv} +@gccoptlist{-msim -mlra -mnodiv -mft32b -mcompress -mnopm} @emph{FRV Options} @gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol @@ -17768,6 +17768,18 @@ so by default the compiler uses standard reload. @opindex mnodiv Do not use div and mod instructions. +@item -mft32b +@opindex mft32b +Enable use of the extended instructions of the FT32B processor. + +@item -mcompress +@opindex mcompress +Compress all code using the Ft32B code compression scheme. + +@item -mnopm +@opindex mnopm +Do not generate code that reads program memory. + @end table @node FRV Options -- 2.30.2