From 7c805a7c670ca588b5c5a17f7563131caf22e81b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 23 May 2019 14:20:27 -0400 Subject: [PATCH] radeonsi/gfx10: set the DCC constant encoding flag Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_pipe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 91b474d4d8f..e25c65abda8 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1124,7 +1124,8 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->info.family == CHIP_RAVEN; sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; - sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2; + sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 || + sscreen->info.chip_class >= GFX10; /* Only enable primitive binning on APUs by default. */ sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN || -- 2.30.2