From 7c809561820e5898d26fa9d3076b892bbfbbff76 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 23 May 2020 09:16:23 -0400 Subject: [PATCH] Add test_isel --- src/soc/fu/cr/test/test_pipe_caller.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 1f2a183e..949238b7 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -125,6 +125,18 @@ class CRTestCase(FHDLTestCase): cr = random.randint(0, (1<<32)-1) self.run_tst_program(Program(lst), initial_cr=cr) + def test_isel(self): + for i in range(20): + bc = random.randint(0, 31) + lst = [f"isel 1, 2, 3, {bc}"] + cr = random.randint(0, (1<<32)-1) + initial_regs = [0] * 32 + initial_regs[2] = random.randint(0, (1<<64)-1) + initial_regs[3] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_cr=cr) + + + def test_ilang(self): pspec = CRPipeSpec(id_wid=2) alu = CRBasePipe(pspec) -- 2.30.2