From 7cbd776f951b6f4a8d31dd9f1cff5c210f98971a Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Aug 2020 13:23:04 +0100
Subject: [PATCH] need to read SO if Rc=1

---
 libreriscv                           |  2 +-
 src/soc/decoder/power_regspec_map.py |  5 ++++-
 src/soc/fu/test/common.py            | 14 ++++++++------
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/libreriscv b/libreriscv
index 1b3c9590..47c09ca2 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 1b3c9590a8878194b8df77c10d184f26f2670ee8
+Subproject commit 47c09ca29544ec2a0ddce960af8b8feb22cf037d
diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 81298e8e..1e6cf3af 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -76,7 +76,10 @@ def regspec_decode_read(e, regfile, name):
         CA = 1<<XERRegs.CA
         OV = 1<<XERRegs.OV
         if name == 'xer_so':
-            return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, SO
+            # SO needs to be read for overflow *and* for creation
+            # of CR0 and also for MFSPR
+            return ((e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in |
+                     (e.do.rc.rc & e.do.rc.ok)), SO
         if name == 'xer_ov':
             return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, OV
         if name == 'xer_ca':
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 2ced9569..bffb4128 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -438,12 +438,14 @@ class ALUHelpers:
             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 
     def get_sim_xer_so(res, sim, dec2):
-        yield
-        #oe = yield dec2.e.do.oe.oe
-        #oe_ok = yield dec2.e.do.oe.ok
-        #xer_in = yield dec2.e.xer_in
-        #if xer_in or (oe and oe_ok):
-        res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+        print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_in = yield dec2.e.xer_in
+        rc = yield dec2.e.do.rc.rc
+        rc_ok = yield dec2.e.do.rc.ok
+        if xer_in or (oe and oe_ok) or (rc and rc_ok):
+            res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 
     def check_slow_spr1(dut, res, sim_o, msg):
         if 'spr1' in res:
-- 
2.30.2