From 7cbdc87dd5c250a5fbf4be81581027438c7bbb94 Mon Sep 17 00:00:00 2001 From: Kirill Yukhin Date: Fri, 22 Aug 2014 09:46:18 +0000 Subject: [PATCH] sse.md (define_mode_iterator V_AVX512VL): Delete. gcc/ * gcc/config/i386/sse.md (define_mode_iterator V_AVX512VL): Delete. (define_mode_iterator V48_AVX512VL): New. (define_mode_iterator V12_AVX512VL): Ditto. (define_insn _load_mask): Split into two similar patterns which use different mode iterators: V48_AVX512VL V12_AVX512VL. Refactor output template. (define_insn "_store_mask"): Ditto. From-SVN: r214307 --- gcc/ChangeLog | 10 +++ gcc/config/i386/sse.md | 146 +++++++++++++++++++++++++---------------- 2 files changed, 98 insertions(+), 58 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d91da012da..7f5555b6759 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2014-08-22 Kirill Yukhin + + * gcc/config/i386/sse.md (define_mode_iterator V_AVX512VL): Delete. + (define_mode_iterator V48_AVX512VL): New. + (define_mode_iterator V12_AVX512VL): Ditto. + (define_insn _load_mask): Split into two similar + patterns which use different mode iterators: V48_AVX512VL V12_AVX512VL. + Refactor output template. + (define_insn "_store_mask"): Ditto. + 2014-08-22 David Malcolm * cprop.c (struct occr): Strengthen field "insn" from rtx to diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 967092e35fb..ca944a33382 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -150,16 +150,17 @@ (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) -;; All AVX512VL vector modes -(define_mode_iterator V_AVX512VL - [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") - (V16QI "TARGET_AVX512VL && TARGET_AVX512BW") - (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") - (V8HI "TARGET_AVX512VL && TARGET_AVX512BW") - (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) +;; All AVX-512{F,VL} vector modes. Supposed TARGET_AVX512F baseline. +(define_mode_iterator V48_AVX512VL + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + +;; 1,2 byte AVX-512{BW,VL} vector modes. Supposed TARGET_AVX512BW baseline. +(define_mode_iterator VI12_AVX512VL + [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) ;; All vector modes (define_mode_iterator V @@ -849,43 +850,56 @@ (const_string "")))]) (define_insn "_load_mask" - [(set (match_operand:V_AVX512VL 0 "register_operand" "=v,v") - (vec_merge:V_AVX512VL - (match_operand:V_AVX512VL 1 "nonimmediate_operand" "v,m") - (match_operand:V_AVX512VL 2 "vector_move_operand" "0C,0C") + [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "v,m") + (match_operand:V48_AVX512VL 2 "vector_move_operand" "0C,0C") (match_operand: 3 "register_operand" "Yk,Yk")))] "TARGET_AVX512F" { - switch (MODE_) + static char buf [64]; + + const char *insn_op; + const char *sse_suffix; + const char *align; + if (FLOAT_MODE_P (GET_MODE_INNER (mode))) { - case MODE_V8DF: - case MODE_V4DF: - case MODE_V2DF: - case MODE_V16SF: - case MODE_V8SF: - case MODE_V4SF: - if (misaligned_operand (operands[1], mode)) - return "vmovu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; - return "vmova\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; - default: - /* There is no vmovdqa8/16 use vmovdqu8/16 instead. */ - if (mode == V64QImode - || mode == V32QImode - || mode == V16QImode - || mode == V32HImode - || mode == V16HImode - || mode == V8HImode - || misaligned_operand (operands[1], mode)) - return "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; - else - return "vmovdqa\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; + insn_op = "vmov"; + sse_suffix = ""; } + else + { + insn_op = "vmovdq"; + sse_suffix = ""; + } + + if (misaligned_operand (operands[1], mode)) + align = "u"; + else + align = "a"; + + snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%3%%}%%N2|%%0%%{%%3%%}%%N2, %%1}", + insn_op, align, sse_suffix); + return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "memory" "none,load") (set_attr "mode" "")]) +(define_insn "_load_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v,m") + (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C,0C") + (match_operand: 3 "register_operand" "Yk,Yk")))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "memory" "none,load") + (set_attr "mode" "")]) + (define_insn "avx512f_blendm" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (vec_merge:VI48F_512 @@ -899,40 +913,56 @@ (set_attr "mode" "")]) (define_insn "_store_mask" - [(set (match_operand:V_AVX512VL 0 "memory_operand" "=m") - (vec_merge:V_AVX512VL - (match_operand:V_AVX512VL 1 "register_operand" "v") + [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "register_operand" "v") (match_dup 0) (match_operand: 2 "register_operand" "Yk")))] "TARGET_AVX512F" { - switch (MODE_) + static char buf [64]; + + const char *insn_op; + const char *sse_suffix; + const char *align; + if (FLOAT_MODE_P (GET_MODE_INNER (mode))) { - case MODE_V8DF: - case MODE_V4DF: - case MODE_V2DF: - case MODE_V16SF: - case MODE_V8SF: - case MODE_V4SF: - return "vmova\t{%1, %0%{%2%}|%0%{%2%}, %1}"; - default: - /* There is no vmovdqa8/16 use vmovdqu8/16 instead. */ - if (mode == V64QImode - || mode == V32QImode - || mode == V16QImode - || mode == V32HImode - || mode == V16HImode - || mode == V8HImode) - return "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; - else - return "vmovdqa\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + insn_op = "vmov"; + sse_suffix = ""; } + else + { + insn_op = "vmovdq"; + sse_suffix = ""; + } + + if (misaligned_operand (operands[1], mode)) + align = "u"; + else + align = "a"; + + snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%2%%}|%%0%%{%%2%%}, %%1}", + insn_op, align, sse_suffix); + return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "memory" "store") (set_attr "mode" "")]) +(define_insn "_store_mask" + [(set (match_operand:VI12_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "register_operand" "v") + (match_dup 0) + (match_operand: 2 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "memory" "store") + (set_attr "mode" "")]) + (define_insn "sse2_movq128" [(set (match_operand:V2DI 0 "register_operand" "=x") (vec_concat:V2DI -- 2.30.2