From 7cc35a30872cbe3932e1fc26a2105b2d0286eab5 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Sat, 14 Nov 2020 16:22:34 +0100 Subject: [PATCH] sim._pyrtl: mask Mux selection operand. Otherwise it behaves funny when it's eg. the result of operator ~. --- nmigen/sim/_pyrtl.py | 2 +- tests/test_sim.py | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/nmigen/sim/_pyrtl.py b/nmigen/sim/_pyrtl.py index f7abc3b..3258f2b 100644 --- a/nmigen/sim/_pyrtl.py +++ b/nmigen/sim/_pyrtl.py @@ -177,7 +177,7 @@ class _RHSValueCompiler(_ValueCompiler): elif len(value.operands) == 3: if value.operator == "m": sel, val1, val0 = value.operands - return f"({self(val1)} if {self(sel)} else {self(val0)})" + return f"({self(val1)} if {mask(sel)} else {self(val0)})" raise NotImplementedError("Operator '{}' not implemented".format(value.operator)) # :nocov: def on_Slice(self, value): diff --git a/tests/test_sim.py b/tests/test_sim.py index d2d255f..bb3906c 100644 --- a/tests/test_sim.py +++ b/tests/test_sim.py @@ -186,6 +186,11 @@ class SimulatorUnitTestCase(FHDLTestCase): self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4)) self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4)) + def test_mux_invert(self): + stmt = lambda y, a, b, c: y.eq(Mux(~c, a, b)) + self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(2, 4)) + self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(3, 4)) + def test_abs(self): stmt = lambda y, a: y.eq(abs(a)) self.assertStatement(stmt, [C(3, unsigned(8))], C(3, unsigned(8))) -- 2.30.2