From 7cc462373f3704daecf8406a589a3f579a51d591 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 7 May 2021 12:19:26 +0100 Subject: [PATCH] move zero-dest-pred in Common Output Stage to not copy target. this then allows CR0 to set a "zero" bit --- src/soc/fu/common_output_stage.py | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 23e83f57..23b270bd 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -52,7 +52,8 @@ class CommonOutputStage(PipeModBase): # comb += target.eq(o[:32]) #with m.Else(): # comb += target.eq(o) - comb += target.eq(o) + with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, target is zero + comb += target.eq(o) # carry-out only if actually present in this input spec # (note: MUL and DIV do not have it, but ALU and Logical do) @@ -87,15 +88,11 @@ class CommonOutputStage(PipeModBase): with m.Else(): comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative)) - with m.If(~op.sv_pred_dz): - # copy out [inverted?] output, cr0, and context out - comb += self.o.o.data.eq(o) - comb += self.o.cr0.data.eq(cr0) # CR0 to be set - - # set output to write + # copy out [inverted?] output, cr0, and context out + comb += self.o.o.data.eq(o) comb += self.o.o.ok.eq(self.i.o.ok) + comb += self.o.cr0.data.eq(cr0) # CR0 to be set comb += self.o.cr0.ok.eq(op.write_cr0) - # context - comb += self.o.ctx.eq(self.i.ctx) + comb += self.o.ctx.eq(self.i.ctx) # context return m -- 2.30.2