From 7ccb4e4e6a16604a91b803e07b549816f5171d37 Mon Sep 17 00:00:00 2001 From: Prachi Godbole Date: Thu, 23 Jul 2015 07:58:20 +0000 Subject: [PATCH] I6400 scheduling. gcc/ * config/mips/i6400.md: New file. * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400. (mips64r6): Likewise. (i6400): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add I6400 processor. (mips_issue_rate): Add support for i6400. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h (TUNE_I6400): Define. * config/mips/mips.md: Include i6400.md. (processor): Add i6400. * doc/invoke.texi (-march=@var{arch}): Add i6400. From-SVN: r226090 --- gcc/ChangeLog | 15 ++++ gcc/config/mips/i6400.md | 142 ++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 7 +- gcc/config/mips/mips-tables.opt | 2 + gcc/config/mips/mips.c | 16 +++- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 1 + 8 files changed, 184 insertions(+), 4 deletions(-) create mode 100644 gcc/config/mips/i6400.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 51649b63c2b..c034124e558 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-07-23 Prachi Godbole + + * config/mips/i6400.md: New file. + * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400. + (mips64r6): Likewise. + (i6400): Define. + * config/mips/mips-tables.opt: Regenerate. + * config/mips/mips.c (mips_rtx_cost_data): Add I6400 processor. + (mips_issue_rate): Add support for i6400. + (mips_multipass_dfa_lookahead): Likewise. + * config/mips/mips.h (TUNE_I6400): Define. + * config/mips/mips.md: Include i6400.md. + (processor): Add i6400. + * doc/invoke.texi (-march=@var{arch}): Add i6400. + 2015-07-23 Richard Biener PR middle-end/66916 diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md new file mode 100644 index 00000000000..a32086f65b7 --- /dev/null +++ b/gcc/config/mips/i6400.md @@ -0,0 +1,142 @@ +;; DFA-based pipeline description for I6400. +;; +;; Copyright (C) 2015 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe, + i6400_fpu_long_pipe") + +(define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe") +(define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe") +(define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe") + +;; Short FPU pipeline. +(define_cpu_unit "i6400_fpu_short" "i6400_fpu_short_pipe") + +;; Long FPU pipeline. +(define_cpu_unit "i6400_fpu_long, i6400_fpu_apu" "i6400_fpu_long_pipe") + +(define_reservation "i6400_control_ctu" "i6400_control, i6400_ctu") +(define_reservation "i6400_control_alu0" "i6400_control, i6400_alu0") +(define_reservation "i6400_agen_lsu" "i6400_agen, i6400_lsu") +(define_reservation "i6400_agen_alu1" "i6400_agen, i6400_alu1") + +;; +;; FPU pipe +;; + +;; fabs, fneg +(define_insn_reservation "i6400_fpu_fabs" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fabs,fneg,fmove")) + "i6400_fpu_short, i6400_fpu_apu") + +;; fadd, fsub, fcvt +(define_insn_reservation "i6400_fpu_fadd" 4 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fadd, fcvt")) + "i6400_fpu_long, i6400_fpu_apu") + +;; fmul +(define_insn_reservation "i6400_fpu_fmul" 5 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fmul")) + "i6400_fpu_long, i6400_fpu_apu") + +;; div, sqrt (Double Precision) +(define_insn_reservation "i6400_fpu_div_df" 30 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "mode" "DF") + (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))) + "i6400_fpu_long+i6400_fpu_apu*30") + +;; div, sqrt (Single Precision) +(define_insn_reservation "i6400_fpu_div_sf" 22 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")) + "i6400_fpu_long+i6400_fpu_apu*22") + +;; +;; Integer pipe +;; + +;; and, lui, shifts, seb, seh +(define_insn_reservation "i6400_int_logical" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "logical,const,andi,sll0,signext")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; addi, addiu, ori, xori, add, addu, sub, nor +(define_insn_reservation "i6400_int_add" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "alu_type" "add,sub,or,xor,nor")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; shifts, clo, clz, cond move, arith +(define_insn_reservation "i6400_int_arith" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "shift,slt,move,clz,condmove,arith")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; nop +(define_insn_reservation "i6400_int_nop" 0 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "nop")) + "nothing") + +;; mult, multu, mul +(define_insn_reservation "i6400_int_mult" 4 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "imul3,imul")) + "i6400_gpmuldiv") + +;; divide +(define_insn_reservation "i6400_int_div" 32 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "idiv")) + "i6400_gpmuldiv*32") + +;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs +(define_insn_reservation "i6400_int_load" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "load")) + "i6400_agen_lsu") + +;; store +(define_insn_reservation "i6400_int_store" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "store")) + "i6400_agen_lsu") + +;; prefetch +(define_insn_reservation "i6400_int_prefetch" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "prefetch")) + "i6400_agen_lsu") + +;; branch and jump +(define_insn_reservation "i6400_int_branch" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "branch,jump")) + "i6400_control_ctu") + +;; call +(define_insn_reservation "i6400_int_call" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "jal" "indirect,direct")) + "i6400_control_ctu") diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 55c0cf6b3f7..e0c77f8f4c9 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -50,13 +50,13 @@ MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY) as mips32r2. */ MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("mips32r6", PROCESSOR_W32, 37, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0) MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY) /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well. */ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("mips64r6", PROCESSOR_W64, 69, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0) /* MIPS I processors. */ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0) @@ -170,3 +170,6 @@ MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY) + +/* MIPS64 Release 6 processors. */ +MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 1f5daa41e94..b83658fdf72 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -693,3 +693,5 @@ Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical EnumValue Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical +EnumValue +Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c3cd52d20b0..bf0f84f5356 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1293,6 +1293,19 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (68), /* int_div_di */ 1, /* branch_cost */ 4 /* memory_latency */ + }, + { /* I6400 */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (5), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (32), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (36), /* int_div_si */ + COSTS_N_INSNS (36), /* int_div_di */ + 2, /* branch_cost */ + 4 /* memory_latency */ } }; @@ -13687,6 +13700,7 @@ mips_issue_rate (void) case PROCESSOR_OCTEON: case PROCESSOR_OCTEON2: case PROCESSOR_OCTEON3: + case PROCESSOR_I6400: return 2; case PROCESSOR_SB1: @@ -13836,7 +13850,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_OCTEON) return 2; - if (TUNE_P5600) + if (TUNE_P5600 || TUNE_I6400) return 4; return 0; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 5bc562e9205..d17a833c743 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -277,6 +277,7 @@ struct mips_cpu_info { #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) +#define TUNE_I6400 (mips_tune == PROCESSOR_I6400) /* Whether vector modes and intrinsics for ST Microelectronics Loongson-2E/2F processors should be enabled. In o32 pairs of @@ -732,7 +733,7 @@ struct mips_cpu_info { %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ - %{march=mips64r6: -mips64r6}}" + %{march=mips64r6|march=i6400: -mips64r6}}" /* A spec that injects the default multilib ISA if no architecture is specified. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index cde2b4eb979..2954a12702b 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -70,6 +70,7 @@ w32 w64 m5100 + i6400 ]) (define_c_enum "unspec" [ @@ -1086,6 +1087,7 @@ (eq_attr "type" "ghost") "nothing") +(include "i6400.md") (include "p5600.md") (include "m5100.md") (include "4k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 413ac1666c8..54e7a679c2f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17041,6 +17041,7 @@ The processor names are: @samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{34kn}, @samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2}, @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, +@samp{i6400}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, -- 2.30.2