From 7ce081d583969bda0690e59ae50ca2d93bb56280 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 4 Jun 2020 10:34:41 +0100 Subject: [PATCH] misc: Remove any reference to the ALPHA ISA Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015 Maintainer: Jason Lowe-Power Reviewed-by: Gabe Black Tested-by: kokoro --- MAINTAINERS | 1 - SConstruct | 2 +- src/arch/mips/idle_event.hh | 6 ++--- src/arch/sparc/kernel_stats.hh | 4 +-- tests/gem5/.testignore | 36 -------------------------- tests/gem5/hello_se/test_hello_se.py | 3 --- tests/testing/tests.py | 11 -------- util/checkpoint-tester.py | 6 ++--- util/compile | 14 +++------- util/cpt_upgraders/isa-is-simobject.py | 1 - util/git-commit-msg.py | 4 +-- 11 files changed, 14 insertions(+), 74 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 436e661bd..9a4d7fc51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -102,7 +102,6 @@ sim-power: Power modeling stats: Updates to statistics for regressions system: System boot code and related components -system-alpha: system-arm: Andreas Sandberg Giacomo Travaglini diff --git a/SConstruct b/SConstruct index 370cd6024..3a03af497 100755 --- a/SConstruct +++ b/SConstruct @@ -988,7 +988,7 @@ all_isa_list.sort() all_gpu_isa_list.sort() sticky_vars.AddVariables( - EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list), + EnumVariable('TARGET_ISA', 'Target ISA', 'null', all_isa_list), EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'hsail', all_gpu_isa_list), ListVariable('CPU_MODELS', 'CPU models', sorted(n for n,m in CpuModel.dict.items() if m.default), diff --git a/src/arch/mips/idle_event.hh b/src/arch/mips/idle_event.hh index 14019189a..d332b872a 100644 --- a/src/arch/mips/idle_event.hh +++ b/src/arch/mips/idle_event.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_MIPS_IDLE_EVENT_HH__ -#define __KERN_MIPS_IDLE_EVENT_HH__ +#ifndef __ARCH_MIPS_IDLE_EVENT_HH__ +#define __ARCH_MIPS_IDLE_EVENT_HH__ #include "cpu/pc_event.hh" @@ -40,4 +40,4 @@ class IdleStartEvent : public PCEvent virtual void process(ThreadContext *tc); }; -#endif // __KERN_ALPHA_IDLE_EVENT_HH__ +#endif // __ARCH_MIPS_IDLE_EVENT_HH__ diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh index 80b8a04a6..41a8dd04d 100644 --- a/src/arch/sparc/kernel_stats.hh +++ b/src/arch/sparc/kernel_stats.hh @@ -46,7 +46,7 @@ class Statistics : public ::Kernel::Statistics {} }; -} // namespace AlphaISA::Kernel -} // namespace AlphaISA +} // namespace SparcISA::Kernel +} // namespace SparcISA #endif // __ARCH_SPARC_KERNEL_STATS_HH__ diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore index b8cfc7f50..c76d7c685 100644 --- a/tests/gem5/.testignore +++ b/tests/gem5/.testignore @@ -93,95 +93,59 @@ test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-fast test-insttest-linux-AtomicSimpleCPU-SPARC-i386-fast test-insttest-linux-TimingSimpleCPU-SPARC-i386-fast test-hello-linux-MinorCPU-RISCV-x86_64-debug -test-hello-linux-MinorCPU-ALPHA-x86_64-debug test-hello-linux-TimingSimpleCPU-SPARC-x86_64-debug test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-debug test-hello-linux-TimingSimpleCPU-MIPS-x86_64-debug test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-debug test-hello-linux-DerivO3CPU-MIPS-x86_64-debug -test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-debug -test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-debug -test-hello-linux-DerivO3CPU-ALPHA-x86_64-debug test-hello-linux-MinorCPU-RISCV-x86_64-fast -test-hello-linux-MinorCPU-ALPHA-x86_64-fast test-hello-linux-TimingSimpleCPU-SPARC-x86_64-fast test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-fast test-hello-linux-TimingSimpleCPU-MIPS-x86_64-fast test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-fast test-hello-linux-DerivO3CPU-MIPS-x86_64-fast -test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-fast -test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-fast -test-hello-linux-DerivO3CPU-ALPHA-x86_64-fast test-hello-linux-MinorCPU-RISCV-x86_64-opt -test-hello-linux-MinorCPU-ALPHA-x86_64-opt test-hello-linux-TimingSimpleCPU-SPARC-x86_64-opt test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-opt test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt test-hello-linux-DerivO3CPU-MIPS-x86_64-opt -test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-opt -test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-opt -test-hello-linux-DerivO3CPU-ALPHA-x86_64-opt test-hello-linux-MinorCPU-RISCV-arch64-debug -test-hello-linux-MinorCPU-ALPHA-arch64-debug test-hello-linux-TimingSimpleCPU-SPARC-arch64-debug test-hello-linux-AtomicSimpleCPU-SPARC-arch64-debug test-hello-linux-TimingSimpleCPU-MIPS-arch64-debug test-hello-linux-AtomicSimpleCPU-MIPS-arch64-debug test-hello-linux-DerivO3CPU-MIPS-arch64-debug -test-hello-linux-TimingSimpleCPU-ALPHA-arch64-debug -test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-debug -test-hello-linux-DerivO3CPU-ALPHA-arch64-debug test-hello-linux-MinorCPU-RISCV-arch64-fast -test-hello-linux-MinorCPU-ALPHA-arch64-fast test-hello-linux-TimingSimpleCPU-SPARC-arch64-fast test-hello-linux-AtomicSimpleCPU-SPARC-arch64-fast test-hello-linux-TimingSimpleCPU-MIPS-arch64-fast test-hello-linux-AtomicSimpleCPU-MIPS-arch64-fast test-hello-linux-DerivO3CPU-MIPS-arch64-fast -test-hello-linux-TimingSimpleCPU-ALPHA-arch64-fast -test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-fast -test-hello-linux-DerivO3CPU-ALPHA-arch64-fast test-hello-linux-MinorCPU-RISCV-arch64-opt -test-hello-linux-MinorCPU-ALPHA-arch64-opt test-hello-linux-TimingSimpleCPU-SPARC-arch64-opt test-hello-linux-AtomicSimpleCPU-SPARC-arch64-opt test-hello-linux-TimingSimpleCPU-MIPS-arch64-opt test-hello-linux-AtomicSimpleCPU-MIPS-arch64-opt test-hello-linux-DerivO3CPU-MIPS-arch64-opt -test-hello-linux-TimingSimpleCPU-ALPHA-arch64-opt -test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-opt -test-hello-linux-DerivO3CPU-ALPHA-arch64-opt test-hello-linux-MinorCPU-RISCV-i386-debug -test-hello-linux-MinorCPU-ALPHA-i386-debug test-hello-linux-TimingSimpleCPU-SPARC-i386-debug test-hello-linux-AtomicSimpleCPU-SPARC-i386-debug test-hello-linux-TimingSimpleCPU-MIPS-i386-debug test-hello-linux-AtomicSimpleCPU-MIPS-i386-debug test-hello-linux-DerivO3CPU-MIPS-i386-debug -test-hello-linux-TimingSimpleCPU-ALPHA-i386-debug -test-hello-linux-AtomicSimpleCPU-ALPHA-i386-debug -test-hello-linux-DerivO3CPU-ALPHA-i386-debug test-hello-linux-MinorCPU-RISCV-i386-fast -test-hello-linux-MinorCPU-ALPHA-i386-fast test-hello-linux-TimingSimpleCPU-SPARC-i386-fast test-hello-linux-AtomicSimpleCPU-SPARC-i386-fast test-hello-linux-TimingSimpleCPU-MIPS-i386-fast test-hello-linux-AtomicSimpleCPU-MIPS-i386-fast test-hello-linux-DerivO3CPU-MIPS-i386-fast -test-hello-linux-TimingSimpleCPU-ALPHA-i386-fast -test-hello-linux-AtomicSimpleCPU-ALPHA-i386-fast -test-hello-linux-DerivO3CPU-ALPHA-i386-fast test-hello-linux-MinorCPU-RISCV-i386-opt -test-hello-linux-MinorCPU-ALPHA-i386-opt test-hello-linux-TimingSimpleCPU-SPARC-i386-opt test-hello-linux-AtomicSimpleCPU-SPARC-i386-opt test-hello-linux-TimingSimpleCPU-MIPS-i386-opt test-hello-linux-AtomicSimpleCPU-MIPS-i386-opt test-hello-linux-DerivO3CPU-MIPS-i386-opt -test-hello-linux-TimingSimpleCPU-ALPHA-i386-opt -test-hello-linux-AtomicSimpleCPU-ALPHA-i386-opt -test-hello-linux-DerivO3CPU-ALPHA-i386-opt test-atomic-DerivO3CPU-SPARC-x86_64-opt test-atomic-TimingSimpleCPU-SPARC-x86_64-opt test-atomic-DerivO3CPU-SPARC-x86_64-debug diff --git a/tests/gem5/hello_se/test_hello_se.py b/tests/gem5/hello_se/test_hello_se.py index 260daad51..96f6d33a3 100644 --- a/tests/gem5/hello_se/test_hello_se.py +++ b/tests/gem5/hello_se/test_hello_se.py @@ -47,7 +47,6 @@ from testlib import * static_progs = { 'x86': ('hello64-static', 'hello32-static'), 'arm': ('hello64-static', 'hello32-static'), - 'alpha': ('hello',), 'mips': ('hello',), 'riscv': ('hello',), 'sparc': ('hello',) @@ -60,7 +59,6 @@ dynamic_progs = { cpu_types = { 'x86': ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU'), 'arm' : ('TimingSimpleCPU', 'AtomicSimpleCPU','DerivO3CPU'), - 'alpha': ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU', 'MinorCPU'), 'mips' : ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU'), 'riscv' : ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU', 'MinorCPU'), 'sparc' : ('TimingSimpleCPU', 'AtomicSimpleCPU') @@ -69,7 +67,6 @@ cpu_types = { supported_os = { 'x86': ('linux',), 'arm' : ('linux',), - 'alpha' : ('linux',), 'mips' : ('linux',), 'riscv' : ('linux',), 'sparc' : ('linux',) diff --git a/tests/testing/tests.py b/tests/testing/tests.py index 042180d79..26f431c8d 100755 --- a/tests/testing/tests.py +++ b/tests/testing/tests.py @@ -81,17 +81,6 @@ ClassicConfig = namedtuple("ClassicConfig", ( # original name. See get_tests() for details. # arch_configs = { - ("alpha", None) : ( - 'tsunami-simple-atomic', - 'tsunami-simple-timing', - 'tsunami-simple-atomic-dual', - 'tsunami-simple-timing-dual', - 'twosys-tsunami-simple-atomic', - 'tsunami-o3', 'tsunami-o3-dual', - 'tsunami-minor', 'tsunami-minor-dual', - 'tsunami-switcheroo-full', - ), - ("arm", None) : ( 'simple-atomic-dummychecker', 'o3-timing-checker', diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py index e7bd45e24..5ad9219be 100755 --- a/util/checkpoint-tester.py +++ b/util/checkpoint-tester.py @@ -55,11 +55,11 @@ # # Examples: # -# util/checkpoint-tester.py -i 400000 -- build/ALPHA_SE/m5.opt \ -# configs/example/se.py -c tests/test-progs/hello/bin/alpha/tru64/hello \ +# util/checkpoint-tester.py -i 400000 -- build//m5.opt \ +# configs/example/se.py -c tests/test-progs/hello/bin//tru64/hello \ # --output=progout --errout=progerr # -# util/checkpoint-tester.py -i 200000000000 -- build/ALPHA_FS/m5.opt \ +# util/checkpoint-tester.py -i 200000000000 -- build//m5.opt \ # configs/example/fs.py --script tests/halt.sh # diff --git a/util/compile b/util/compile index 1ef3f2cca..ce2b4188e 100755 --- a/util/compile +++ b/util/compile @@ -155,7 +155,6 @@ add_option('-a', "--all-bin", default=False, action='store_true', help="compile debug, opt, and fast binaries") set_group("ISA options") -bool_option("alpha", default=False, help="compile Alpha") bool_option("mips", default=False, help="compile MIPS") bool_option("sparc", default=False, help="compile SPARC") add_option('-i', "--all-isa", default=False, action='store_true', @@ -198,21 +197,15 @@ if not binaries: binaries.append('m5.debug') if options.all_isa: - options.alpha = True options.mips = True options.sparc = True isas = [] -if options.alpha: - isas.append('alpha') if options.mips: isas.append('mips') if options.sparc: isas.append('sparc') -if not isas: - isas.append('alpha') - modes = [] if options.syscall: modes.append('syscall') @@ -227,10 +220,9 @@ if not modes: # # valid combinations of ISA and emulation mode -valid = { ('alpha', 'syscall') : 'ALPHA_SE', - ('alpha', 'fullsys') : 'ALPHA_FS', - ('mips', 'syscall') : 'MIPS_SE', - ('sparc', 'syscall') : 'SPARC_SE' } +valid = { + ('mips', 'syscall') : 'MIPS_SE', + ('sparc', 'syscall') : 'SPARC_SE' } # experimental combinations of ISA and emulation mode experiment = { ('mips', 'fullsys') : 'MIPS_FS', diff --git a/util/cpt_upgraders/isa-is-simobject.py b/util/cpt_upgraders/isa-is-simobject.py index 8633bf0ed..72c62568a 100644 --- a/util/cpt_upgraders/isa-is-simobject.py +++ b/util/cpt_upgraders/isa-is-simobject.py @@ -3,7 +3,6 @@ def upgrader(cpt): isa = cpt.get('root','isa') isa_fields = { - "alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ), "arm" : ( "miscRegs" ), "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr", "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt", diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py index 92e8100be..500c5c71d 100755 --- a/util/git-commit-msg.py +++ b/util/git-commit-msg.py @@ -88,13 +88,13 @@ def _validateTags(commit_header): # @todo this is error prone, and should be extracted automatically from # a file - valid_tags = ["arch", "arch-alpha", "arch-arm", "arch-gcn3", "arch-hsail", + valid_tags = ["arch", "arch-arm", "arch-gcn3", "arch-hsail", "arch-mips", "arch-power", "arch-riscv", "arch-sparc", "arch-x86", "base", "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3", "cpu-simple", "dev", "dev-arm", "dev-virtio", "ext", "fastmodel", "gpu-compute", "learning-gem5", "mem", "mem-cache", "mem-garnet", "mem-ruby", "misc", "python", "scons", "sim", "sim-se", "sim-power", - "stats", "system", "system-alpha", "system-arm", "systemc", "tests", + "stats", "system", "system-arm", "systemc", "tests", "util", "RFC", "WIP"] tags = ''.join(commit_header.split(':')[0].split()).split(',') -- 2.30.2