From 7cf0b2e637c02053a1a23c5a643e8c6b1c5bb942 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 23:38:17 +0000 Subject: [PATCH] comments on sv.add. Rc=1 unit test --- src/soc/decoder/isa/test_caller_svp64.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index 27a21526..676a87d1 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -107,9 +107,9 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def test_sv_add_cr(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + # adds when Rc=1: TODO CRs higher up + # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 + # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v' ]) lst = list(isa) -- 2.30.2