From 7d03c95d9c79555f90e6e82dd435e86bd851d902 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 18 Mar 2020 18:22:14 +0000 Subject: [PATCH] Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V --- 51/316eb8ff3b0c765fd273f4273c30915bd59e59 | 91 +++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 51/316eb8ff3b0c765fd273f4273c30915bd59e59 diff --git a/51/316eb8ff3b0c765fd273f4273c30915bd59e59 b/51/316eb8ff3b0c765fd273f4273c30915bd59e59 new file mode 100644 index 0000000..cec369a --- /dev/null +++ b/51/316eb8ff3b0c765fd273f4273c30915bd59e59 @@ -0,0 +1,91 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 18 Mar 2020 18:22:38 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jEdKv-0003AF-BN; Wed, 18 Mar 2020 18:22:37 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jEdKu-0003A8-IY + for libre-riscv-dev@lists.libre-riscv.org; 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