From 7d0f8643e17855f5cbdb3b7e93e78badd3ad08cb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 24 Jun 2019 12:55:30 +0100 Subject: [PATCH] update STATE format (bit error) --- simple_v_extension/specification.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 1a2443a73..8d509ea85 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -322,7 +322,7 @@ and seSTATE). The format of the STATE CSR is as follows: -| (30..29 | (28..27) | (26..24) | (23..18) | (17..12) | (11..6) | (5...0) | +| (29..28 | (27..26) | (25..24) | (23..18) | (17..12) | (11..6) | (5...0) | | ------- | -------- | -------- | -------- | -------- | ------- | ------- | | dsvoffs | ssvoffs | subvl | destoffs | srcoffs | vl | maxvl | @@ -2594,6 +2594,11 @@ Could the 8 bit Register VLIW format use regnum<<1 instead, only accessing regs -- +Expand the range of SUBVL and its associated svsrcoffs and svdestoffs by +adding a 2nd STATE CSR (or extending STATE to 64 bits). Future version? + +-- + TODO evaluate strncpy and strlen -- 2.30.2