From 7d313da3b5c8d67f680b4ddbd89be4a14ab6c0cf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 May 2020 15:52:35 +0100 Subject: [PATCH] whoops cant output .il at the moment --- src/ieee754/cordic/test/test_fp_pipe.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py index ee18ff21..22d2f20a 100644 --- a/src/ieee754/cordic/test/test_fp_pipe.py +++ b/src/ieee754/cordic/test/test_fp_pipe.py @@ -18,9 +18,11 @@ class SinCosTestCase(FHDLTestCase): m.submodules.dut = dut = FPCordicBasePipe(pspec) # write out module (useful for seeing what's going on) - vl = rtlil.convert(dut, ports=dut.ports()) - with open("test_cordic_pipe_sin_cos.il", "w") as f: - f.write(vl) + # XXX WHOOPS can't do this at the moment, need to track down + # an issue in the ports + # vl = rtlil.convert(dut, ports=dut.ports()) + # with open("test_cordic_pipe_sin_cos.il", "w") as f: + # f.write(vl) z = Signal(dut.p.data_i.a.shape()) z_valid = Signal() -- 2.30.2