From 7d371ee3f48d0e8db097830a9ae1a3b1fd0c939e Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Wed, 29 Jul 2020 18:49:50 +0200 Subject: [PATCH] Remove datavalid signal --- gram/phy/ecp5ddrphy.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 394e652..eb4c7b1 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -156,9 +156,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable): cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) - # Observation - self.datavalid = Signal(databits//8) - # DFI Interface ---------------------------------------------------------------------------- dfi = self.dfi @@ -280,7 +277,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable): o_WRPNTR0=wrpntr[0], o_WRPNTR1=wrpntr[1], o_WRPNTR2=wrpntr[2], - o_DATAVALID=self.datavalid[i], o_BURSTDET=burstdet, # Writes (generate shifted ECLK clock for writes) -- 2.30.2