From 7d3f7f277ac1951c5f6d243b9c13091c45cc467d Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 14 Dec 2018 13:30:09 +0000 Subject: [PATCH] back.pysim: accept (and evaluate) generator functions. --- nmigen/back/pysim.py | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 88cd7a3..469ef4b 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -1,4 +1,5 @@ import math +import inspect from vcd import VCDWriter from vcd.gtkw import GTKWSave @@ -223,9 +224,30 @@ class Simulator: self._gtkw_file = gtkw_file self._gtkw_signals = gtkw_signals + def _check_process(self, process): + if inspect.isgeneratorfunction(process): + process = process() + if not inspect.isgenerator(process): + raise TypeError("Cannot add a process '{!r}' because it is not a generator or" + "a generator function" + .format(process)) + return process + def add_process(self, process): + process = self._check_process(process) self._processes.add(process) + def add_sync_process(self, process, domain="sync"): + process = self._check_process(process) + def sync_process(): + try: + result = process.send(None) + while True: + result = process.send((yield (result or Tick(domain)))) + except StopIteration: + pass + self.add_process(sync_process()) + def add_clock(self, period, domain="sync"): if self._fastest_clock == self._epsilon or period < self._fastest_clock: self._fastest_clock = period @@ -242,16 +264,6 @@ class Simulator: yield Delay(half_period) self.add_process(clk_process()) - def add_sync_process(self, process, domain="sync"): - def sync_process(): - try: - result = process.send(None) - while True: - result = process.send((yield (result or Tick(domain)))) - except StopIteration: - pass - self.add_process(sync_process()) - def __enter__(self): if self._vcd_file: self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps", -- 2.30.2