From 7d494e2b0299f26bbc5898ef6279138cef64bb72 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 May 2021 18:34:42 +0100
Subject: [PATCH] add demo --load option to pypowersim

---
 src/openpower/decoder/isa/mem.py        | 11 ++++++-
 src/openpower/decoder/isa/pypowersim.py | 44 +++++++++++++++++++++----
 src/test/basic_pypowersim/Makefile      |  6 ++--
 3 files changed, 52 insertions(+), 9 deletions(-)

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index 64309477..008370a9 100644
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -132,4 +132,13 @@ class Mem:
         print("memassign", addr, sz, val)
         self.st(addr.value, val.value, sz, swap=False)
 
-
+    def dump(self, printout=True):
+        keys = list(self.mem.keys())
+        keys.sort()
+        res = []
+        for k in keys:
+            res.append(((k*8), self.mem[k]))
+            if not printout:
+                continue
+            print ("%016x: %016x" % ((k*8) & 0xffffffffffffffff, self.mem[k]))
+        return res
diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 1c631630..83831a66 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -2,6 +2,7 @@ from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
 import sys
 import getopt
+import struct
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
@@ -10,6 +11,21 @@ from openpower.decoder.orderedset import OrderedSet
 from openpower.decoder.isa.all import ISA
 
 
+def read_data(fname, offset=0):
+    """reads binary data and returns a dictionary of address: contents,
+    each entry is 8 bytes. input file *must* be 8-byte-aligned
+    """
+    res = {}
+    with open(fname, "rb") as f:
+        while True:
+            b = f.read(8)
+            print (repr(b))
+            if not b:
+                return res
+            res[offset] = struct.unpack('<Q', b)[0] # unsigned long
+            offset += 8
+
+
 def convert_to_num(num):
     # detect number types
     if num.isdigit():
@@ -51,7 +67,7 @@ def read_entries(fname, listqty=None):
     return result
 
 
-def run_tst(args, generator, initial_regs, 
+def run_tst(args, generator, initial_regs,
                              initial_sprs=None, svstate=0, mmu=False,
                              initial_cr=0, mem=None,
                              initial_fprs=None):
@@ -132,13 +148,15 @@ def run_simulation():
     initial_regs = None
     initial_fprs = None
     initial_sprs = None
+    initial_mem = {}
     lst = None
 
     try:
-        opts, args = getopt.getopt(sys.argv[1:], "i:l:g:f:s:", 
-                                   ["binary", "listing",
-                                    "intregs", "fpregs", "sprs"])
-      
+        opts, args = getopt.getopt(sys.argv[1:], "i:l:g:f:s:l:",
+                                   ["binary=", "listing=",
+                                    "intregs=", "fpregs=", "sprs=",
+                                    "load="])
+
     except:
         sys.stderr.write("Command-line Error\n")
         help()
@@ -154,6 +172,18 @@ def run_simulation():
             initial_fprs = read_entries(arg, 32)
         elif opt in ['-s', '--sprs']:
             initial_sprs = read_entries(arg, 32)
+        elif opt in ['-l', '--load']:
+            arg = list(map(str.strip, arg.split(":")))
+            if len(arg) == 1:
+                fname, offs = arg[0], 0
+            else:
+                fname, offs = arg
+            offs = int(offs)
+            print ("offs load", fname, offs)
+            mem = read_data(fname, offs)
+            initial_mem.update(mem)
+
+    print (initial_mem)
 
     if binaryname is None and lst is None:
         sys.stderr.write("Must give binary or listing\n")
@@ -172,7 +202,7 @@ def run_simulation():
                             initial_regs,
                             initial_sprs=initial_sprs,
                             svstate=0, mmu=False,
-                            initial_cr=0, mem=None,
+                            initial_cr=0, mem=initial_mem,
                             initial_fprs=initial_fprs)
         print ("GPRs")
         simulator.gpr.dump()
@@ -180,6 +210,8 @@ def run_simulation():
         simulator.fpr.dump()
         print ("SPRs")
         simulator.spr.dump()
+        print ("Mem")
+        simulator.mem.dump()
 
 
 if __name__ == "__main__":
diff --git a/src/test/basic_pypowersim/Makefile b/src/test/basic_pypowersim/Makefile
index afd15f33..b9ef925e 100644
--- a/src/test/basic_pypowersim/Makefile
+++ b/src/test/basic_pypowersim/Makefile
@@ -6,12 +6,14 @@ AFLAGS=-mpwr9
 all: sim
 
 sim: kernel.bin
-	pypowersim -g gpr.list -i kernel.bin
+	echo -n -e \\0060\\0000\\0061\\0000 > test.bin
+	echo -n -e \\0060\\0000\\0061\\0000 >> test.bin
+	pypowersim --load test.bin:0 -g gpr.list -i kernel.bin
 
 clean:
 	rm *.o *.elf *.bin
 
-kernel.elf: square.o
+kernel.elf: test.o
 	$(TOOLCHAIN)-ld $^ -EL -o $@ -T memmap
 
 kernel.bin: kernel.elf
-- 
2.30.2