From 7d6e586df8128d4265499ef3f61c1a85ff3cc02a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Dec 2014 15:08:02 +0100 Subject: [PATCH] Added bool constructors to SigBit and SigSpec --- kernel/rtlil.cc | 10 ++++++++++ kernel/rtlil.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2f2f7c704..f5dbafe16 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2188,6 +2188,16 @@ RTLIL::SigSpec::SigSpec(std::set bits) check(); } +RTLIL::SigSpec::SigSpec(bool bit) +{ + cover("kernel.rtlil.sigspec.init.bool"); + + width_ = 0; + hash_ = 0; + append_bit(bit); + check(); +} + void RTLIL::SigSpec::pack() const { RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a488d3a6b..0157f3b7c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -899,6 +899,7 @@ struct RTLIL::SigBit SigBit() : wire(NULL), data(RTLIL::State::S0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } + SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { } SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } @@ -982,6 +983,7 @@ public: SigSpec(std::vector chunks); SigSpec(std::vector bits); SigSpec(std::set bits); + SigSpec(bool bit); SigSpec(RTLIL::SigSpec &&other) { width_ = other.width_; -- 2.30.2