From 7da7269a693f7bb2c3728002dd88b51e3ffa2f8b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 23 Mar 2016 10:49:12 +0100 Subject: [PATCH] re PR target/70321 (STV generates less optimized code) PR target/70321 * config/i386/i386.md (*anddi3_doubleword, *di3_doubleword): Optimize TARGET_STV splitters, if high or low word of last argument is 0 or -1. From-SVN: r234416 --- gcc/ChangeLog | 7 ++++ gcc/config/i386/i386.md | 72 ++++++++++++++++++++++++++++++++--------- 2 files changed, 63 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a7f7933ac79..6261b3a8162 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-03-23 Jakub Jelinek + + PR target/70321 + * config/i386/i386.md (*anddi3_doubleword, *di3_doubleword): + Optimize TARGET_STV splitters, if high or low word of last argument + is 0 or -1. + 2016-03-22 Jeff Law PR target/70232 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index dcaef843900..51e9a6eb75a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8141,16 +8141,31 @@ (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 && ix86_binary_operator_ok (AND, DImode, operands)" + "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 + && ix86_binary_operator_ok (AND, DImode, operands)" "#" "&& reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_dup 3) - (and:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC FLAGS_REG))])] - "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + [(const_int 0)] +{ + split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); + if (operands[2] == const0_rtx) + { + operands[1] = const0_rtx; + ix86_expand_move (SImode, &operands[0]); + } + else if (operands[2] != constm1_rtx) + emit_insn (gen_andsi3 (operands[0], operands[1], operands[2])); + else if (operands[5] == constm1_rtx) + emit_note (NOTE_INSN_DELETED); + if (operands[5] == const0_rtx) + { + operands[4] = const0_rtx; + ix86_expand_move (SImode, &operands[3]); + } + else if (operands[5] != constm1_rtx) + emit_insn (gen_andsi3 (operands[3], operands[4], operands[5])); + DONE; +}) (define_insn "*andsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k") @@ -8665,16 +8680,41 @@ (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 && ix86_binary_operator_ok (, DImode, operands)" + "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 + && ix86_binary_operator_ok (, DImode, operands)" "#" "&& reload_completed" - [(parallel [(set (match_dup 0) - (any_or:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_dup 3) - (any_or:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC FLAGS_REG))])] - "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + [(const_int 0)] +{ + split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); + if (operands[2] == constm1_rtx) + { + if ( == IOR) + { + operands[1] = constm1_rtx; + ix86_expand_move (SImode, &operands[0]); + } + else + ix86_expand_unary_operator (NOT, SImode, &operands[0]); + } + else if (operands[2] != const0_rtx) + ix86_expand_binary_operator (, SImode, &operands[0]); + else if (operands[5] == const0_rtx) + emit_note (NOTE_INSN_DELETED); + if (operands[5] == constm1_rtx) + { + if ( == IOR) + { + operands[4] = constm1_rtx; + ix86_expand_move (SImode, &operands[3]); + } + else + ix86_expand_unary_operator (NOT, SImode, &operands[3]); + } + else if (operands[5] != const0_rtx) + ix86_expand_binary_operator (, SImode, &operands[3]); + DONE; +}) (define_insn_and_split "*andndi3_doubleword" [(set (match_operand:DI 0 "register_operand" "=r,r") -- 2.30.2