From 7dad1f35c256d6518a7e83dfe7330700586ce240 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 13 May 2021 20:02:00 +0100 Subject: [PATCH] yet more debug log stuff for DCache, this time on CacheRam, to discern which SRAM the read/write request went to --- src/soc/experiment/cache_ram.py | 12 ++++++++---- src/soc/experiment/dcache.py | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py index 71dc89ca..50ee1367 100644 --- a/src/soc/experiment/cache_ram.py +++ b/src/soc/experiment/cache_ram.py @@ -4,7 +4,9 @@ from nmutil.util import Display class CacheRam(Elaboratable): - def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False): + def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False, + ram_num=0): + self.ram_num = ram_num # for debug reporting self.ROW_BITS = ROW_BITS self.WIDTH = WIDTH self.TRACE = TRACE @@ -33,8 +35,10 @@ class CacheRam(Elaboratable): with m.If(TRACE): with m.If(self.wr_sel.bool()): - sync += Display( "write a: %x sel: %x dat: %x", - self.wr_addr, self.wr_sel, self.wr_data) + sync += Display( "write ramno %d a: %%x " + "sel: %%x dat: %%x" % self.ram_num, + self.wr_addr, + self.wr_sel, self.wr_data) for i in range(WIDTH//8): lbit = i * 8; mbit = lbit + 8; @@ -43,7 +47,7 @@ class CacheRam(Elaboratable): with m.If(self.rd_en): sync += rd_data0.eq(ram[self.rd_addr]) if TRACE: - sync += Display("read a: %x dat: %x", + sync += Display("read ramno %d a: %%x dat: %%x" % self.ram_num, self.rd_addr, ram[self.rd_addr]) pass diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 54981d75..072d34a9 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1124,7 +1124,7 @@ class DCache(Elaboratable): wr_sel_m = Signal(ROW_SIZE) _d_out = Signal(WB_DATA_BITS, name="dout_%d" % i) # cache_row_t - way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True) + way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True, ram_num=i) setattr(m.submodules, "cacheram_%d" % i, way) comb += way.rd_en.eq(do_read) -- 2.30.2