From 7db144bf9a422906519a9c2b544795e0cb104d24 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Apr 2019 02:03:48 +0100
Subject: [PATCH] reorganise FIFOtest, call it FIFOControl

---
 src/add/singlepipe.py    | 40 ++++++++++++++--------------------------
 src/add/test_buf_pipe.py |  6 +++---
 2 files changed, 17 insertions(+), 29 deletions(-)

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 8296bf2d..e32a0536 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -1014,22 +1014,23 @@ class RegisterPipeline(UnbufferedPipeline):
         UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn))
 
 
-class FIFOtest(ControlBase):
-    """ A test of using a SyncFIFO to see if it will work.
-        Note: the only things it will accept is a Signal of width "width".
+class FIFOControl(ControlBase):
+    """ FIFO Control.  Uses SyncFIFO to store data, coincidentally
+        happens to have same valid/ready signalling as Stage API.
+
+        i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
     """
 
-    def __init__(self, iospecfn, width, depth):
+    def __init__(self, iospecfn, depth):
+        """ * iospecfn: specification for incoming and outgoing data
+            * depth   : number of entries in the FIFO
 
-        self.iospecfn = iospecfn
-        self.fwidth = width # XXX temporary
-        self.fdepth = depth
-        #stage = PassThroughStage(iospecfn)
-        ControlBase.__init__(self, stage=self)
+            NOTE: FPGAs may have trouble with the defaults for SyncFIFO
+        """
 
-    def ispec(self): return self.iospecfn()
-    def ospec(self): return Signal(self.fwidth, name="dout")
-    def process(self, i): return i
+        self.fdepth = depth
+        stage = PassThroughStage(iospecfn)
+        ControlBase.__init__(self, stage=stage)
 
     def elaborate(self, platform):
         self.m = m = ControlBase._elaborate(self, platform)
@@ -1038,8 +1039,7 @@ class FIFOtest(ControlBase):
         fifo = SyncFIFO(fwidth, self.fdepth)
         m.submodules.fifo = fifo
 
-        # XXX TODO: would be nice to do these...
-        ## prev: make the FIFO "look" like a PrevControl...
+        # prev: make the FIFO "look" like a PrevControl...
         fp = PrevControl()
         fp.i_valid = fifo.we
         fp._o_ready = fifo.writable
@@ -1054,18 +1054,6 @@ class FIFOtest(ControlBase):
         # ... so we can do this!
         m.d.comb += fn._connect_out(self.n, fn=flatten)
 
-        # connect previous rdy/valid/data - do flatten on i_data
-        #m.d.comb += [fifo.we.eq(self.p.i_valid_test),
-        #             self.p.o_ready.eq(fifo.writable),
-        #             eq(fifo.din, flatten(self.p.i_data)),
-        #           ]
-
-        # connect next rdy/valid/data - do flatten on o_data
-        #m.d.comb += [self.n.o_valid.eq(fifo.readable),
-        #             fifo.re.eq(self.n.i_ready_test),
-        #             flatten(self.n.o_data).eq(fifo.dout),
-        #           ]
-
         # err... that should be all!
         return m
 
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 6bf690c2..840904c6 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -28,7 +28,7 @@ from singlepipe import UnbufferedPipeline2
 from singlepipe import SimpleHandshake
 from singlepipe import PassThroughHandshake
 from singlepipe import PassThroughStage
-from singlepipe import FIFOtest
+from singlepipe import FIFOControl
 
 from random import randint, seed
 
@@ -766,11 +766,11 @@ class ExampleBufPassThruPipe(ControlBase):
 def iospecfn():
     return Signal(16, name="din")
 
-class FIFOTest16(FIFOtest):
+class FIFOTest16(FIFOControl):
 
 
     def __init__(self):
-        FIFOtest.__init__(self, iospecfn, 16, 2)
+        FIFOControl.__init__(self, iospecfn, 2)
 
 
 ######################################################################
-- 
2.30.2