From 7dc79cdd5a6929d4af9f5e13fb5198397591ba8c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 11:35:30 +0100
Subject: [PATCH] add an extra domain dramsync2x in preparation for AsyncBridge

---
 src/ecp5_crg.py | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 1740169..239a5e6 100644
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -279,5 +279,11 @@ class ECP5CRG(Elaboratable):
         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
         m.d.comb += ResetSignal("dramsync").eq(reset_ok)
 
+        # and a dram 2x sigh
+        cd_dramsync2x = ClockDomain("dramsync2x", local=False)
+        m.domains += cd_dramsync2x
+        m.d.comb += ClockSignal("dramsync2x").eq(ClockSignal("sync2x"))
+        m.d.comb += ResetSignal("dramsync2x").eq(reset_ok)
+
         return m
 
-- 
2.30.2