From 7dd0e8aadb2043e42621dfcb481a148f0e0ad636 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Jun 2021 10:39:32 +0100
Subject: [PATCH] move D const update to after picking up main input registers

---
 src/openpower/decoder/isa/caller.py | 60 +++++++++++++++--------------
 1 file changed, 31 insertions(+), 29 deletions(-)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 141b6889..d1e6bd99 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1152,8 +1152,38 @@ class ISACaller:
                                        self.namespace['NIA'])
             return
 
+        # main input registers (RT, RA ...)
+        inputs = []
+        for name in input_names:
+            # using PowerDecoder2, first, find the decoder index.
+            # (mapping name RA RB RC RS to in1, in2, in3)
+            regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
+            if regnum is None:
+                # doing this is not part of svp64, it's because output
+                # registers, to be modified, need to be in the namespace.
+                regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+            if regnum is None:
+                regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2,
+                                                                 name)
+
+            # in case getting the register number is needed, _RA, _RB
+            regname = "_" + name
+            self.namespace[regname] = regnum
+            if not self.is_svp64_mode or not pred_src_zero:
+                log('reading reg %s %s' % (name, str(regnum)), is_vec)
+                if name in fregs:
+                    reg_val = self.fpr(regnum)
+                else:
+                    reg_val = self.gpr(regnum)
+            else:
+                log('zero input reg %s %s' % (name, str(regnum)), is_vec)
+                reg_val = 0
+            inputs.append(reg_val)
+
         # in SVP64 mode for LD/ST work out immediate
-        replace_d = False # replace constant in pseudocode
+        # XXX TODO: replace_ds for DS-Form rather than D-Form.
+        # use info.form to detect
+        replace_d = False # update / replace constant in pseudocode
         if self.is_svp64_mode:
             D = yield self.dec2.dec.fields.FormD.D[0:16]
             D = exts(D, 16) # sign-extend to integer
@@ -1183,34 +1213,6 @@ class ISACaller:
         if replace_d:
             self.namespace['D'] = D
 
-        # main input registers (RT, RA ...)
-        inputs = []
-        for name in input_names:
-            # using PowerDecoder2, first, find the decoder index.
-            # (mapping name RA RB RC RS to in1, in2, in3)
-            regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
-            if regnum is None:
-                # doing this is not part of svp64, it's because output
-                # registers, to be modified, need to be in the namespace.
-                regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
-            if regnum is None:
-                regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2,
-                                                                 name)
-
-            # in case getting the register number is needed, _RA, _RB
-            regname = "_" + name
-            self.namespace[regname] = regnum
-            if not self.is_svp64_mode or not pred_src_zero:
-                log('reading reg %s %s' % (name, str(regnum)), is_vec)
-                if name in fregs:
-                    reg_val = self.fpr(regnum)
-                else:
-                    reg_val = self.gpr(regnum)
-            else:
-                log('zero input reg %s %s' % (name, str(regnum)), is_vec)
-                reg_val = 0
-            inputs.append(reg_val)
-
         # "special" registers
         for special in info.special_regs:
             if special in special_sprs:
-- 
2.30.2