From 7dfdcd62ae4954ec42075da82b0a140a1e05aa98 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Tue, 18 Jun 2019 13:53:22 +0530 Subject: [PATCH] arch-power: Set initial register state before loading OPAL Change-Id: If4d753a96652e3bde5b2a992d64def64138ac518 Signed-off-by: Kajol Jain --- src/arch/power/isa/decoder.isa | 1 + src/arch/power/system.cc | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3c0a4baa0..61f14ee56 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -624,6 +624,7 @@ decode PO default Unknown::unknown() { 0x3a1: mfiamr({{Rt = IAMR;}}); 0x3a4: mfuamor({{ Rt = UAMOR; }}, [ IsPrivileged ]); 0x3aa: mfamor({{Rt = AMOR;}}); + 0x3a9: mfspr({{ }}); 0x3c5: mfhfscr({{Rt = HFSCR;}}); 0x3c9: mflpcr({{Rt = LPCR;}}); 0x3E8: mfpvr({{ Rt = PVR; }}); diff --git a/src/arch/power/system.cc b/src/arch/power/system.cc index 2acee2695..32580d15f 100644 --- a/src/arch/power/system.cc +++ b/src/arch/power/system.cc @@ -87,7 +87,11 @@ PowerSystem::initState() tc->setIntReg(ArgumentReg0, 0x1800000); ThreadID tid = 1; ThreadContext *tc1 = threadContexts[tid]; - tc1->pcState(0xc00000000000a840); - tc1->setIntReg(ArgumentReg0, 0x1); + tc1->pcState(0x10); + tc1->setIntReg(INTREG_PVR , 0x004e0200); + tc1->setIntReg(INTREG_MSR , msr); + tc1->setIntReg(ArgumentReg0, 0x1800000); + //tc1->pcState(0xc00000000000a840); + //tc1->setIntReg(ArgumentReg0, 0x1); tc1->setIntReg(INTREG_PIR,0x1); } -- 2.30.2