From 7e08e19030fe87f00af88372c2fea23c1b8f0ac1 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Tue, 31 Oct 2000 21:50:30 +0100 Subject: [PATCH] i386.h: Clarify CCNOmode description in comment. * config/i386/i386.h: Clarify CCNOmode description in comment. (EXTRA_CC_MODES): Remove CCRCmode. * config/i386/i386.c (ix86_comparison_operator): Remove CCRCmode. (put_condition_code, ix86_match_ccmode): Likewise. (ix86_cc_mode): Likewise. Fix comment. (ix86_expand_strlensi_unroll_1): *rc patterns are gone. * config/i386/i386.md: Add unspec 12 description. (adddi3 split): Use unspec 12 instead of CCRCmode. (addsi3_carry_rc): Remove. (addsi3_cc, addqi3_cc): New patterns. (addsi_3): Swap operands, match CCZmode. (addsi_4): Rewritten. (addsi_5): Renamed from addsi_6. (addsi_6): Removed. (addhi_3): Swap operands, match CCZmode. (addhi_4): Rewritten. (addhi_5): Renamed from addhi_6. (addhi_6): Removed. (addqi_3): Swap operands, match CCZmode. (addqi_4): Rewritten. (addqi_5): Renamed from addqi_6. Use =q constraint for clobber. (subsi3_carry_rc): Removed. (iorqi_3): Use =q constraint for clobber. (xorqi_cc_2): Likewise. (negdi2_1 split): Don't use CCRCmode, use ltu instead of gtu. (x86_movsicc_0_m1_rc): Removed. (cmp?i peepholes): Remove neg. Use CCGCmode instead of CCRCmode. Co-Authored-By: Jakub Jelinek From-SVN: r37166 --- gcc/ChangeLog | 31 ++++ gcc/config/i386/i386.c | 56 +++----- gcc/config/i386/i386.h | 10 +- gcc/config/i386/i386.md | 308 +++++++++++++++++++++------------------- 4 files changed, 216 insertions(+), 189 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7c617b8b494..3c48642316a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,34 @@ +2000-10-31 Jan Hubicka + Jakub Jelinek + + * config/i386/i386.h: Clarify CCNOmode description in comment. + (EXTRA_CC_MODES): Remove CCRCmode. + * config/i386/i386.c (ix86_comparison_operator): Remove CCRCmode. + (put_condition_code, ix86_match_ccmode): Likewise. + (ix86_cc_mode): Likewise. Fix comment. + (ix86_expand_strlensi_unroll_1): *rc patterns are gone. + * config/i386/i386.md: Add unspec 12 description. + (adddi3 split): Use unspec 12 instead of CCRCmode. + (addsi3_carry_rc): Remove. + (addsi3_cc, addqi3_cc): New patterns. + (addsi_3): Swap operands, match CCZmode. + (addsi_4): Rewritten. + (addsi_5): Renamed from addsi_6. + (addsi_6): Removed. + (addhi_3): Swap operands, match CCZmode. + (addhi_4): Rewritten. + (addhi_5): Renamed from addhi_6. + (addhi_6): Removed. + (addqi_3): Swap operands, match CCZmode. + (addqi_4): Rewritten. + (addqi_5): Renamed from addqi_6. Use =q constraint for clobber. + (subsi3_carry_rc): Removed. + (iorqi_3): Use =q constraint for clobber. + (xorqi_cc_2): Likewise. + (negdi2_1 split): Don't use CCRCmode, use ltu instead of gtu. + (x86_movsicc_0_m1_rc): Removed. + (cmp?i peepholes): Remove neg. Use CCGCmode instead of CCRCmode. + 2000-10-31 Joseph S. Myers * c-typeck.c (build_unary_op): If pedantic, pedwarn for increment diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 078eea0408d..b27edaaf811 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1305,22 +1305,18 @@ ix86_comparison_operator (op, mode) return 1; case LT: case GE: inmode = GET_MODE (XEXP (op, 0)); - if (inmode == CCmode || inmode == CCGCmode || inmode == CCRCmode + if (inmode == CCmode || inmode == CCGCmode || inmode == CCGOCmode || inmode == CCNOmode) return 1; return 0; - case LTU: case GTU: - inmode = GET_MODE (XEXP (op, 0)); - return inmode == CCmode; - case LEU: case ORDERED: case UNORDERED: case GEU: + case LTU: case GTU: case LEU: case ORDERED: case UNORDERED: case GEU: inmode = GET_MODE (XEXP (op, 0)); - if (inmode == CCmode || inmode == CCRCmode) + if (inmode == CCmode) return 1; return 0; case GT: case LE: inmode = GET_MODE (XEXP (op, 0)); - if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode - || inmode == CCRCmode) + if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode) return 1; return 0; default: @@ -3112,22 +3108,21 @@ put_condition_code (code, mode, reverse, fp, file) suffix = "ne"; break; case GT: - if (mode != CCmode && mode != CCNOmode && mode != CCGCmode - && mode != CCRCmode) + if (mode != CCmode && mode != CCNOmode && mode != CCGCmode) abort (); suffix = "g"; break; case GTU: /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers. Those same assemblers have the same but opposite losage on cmov. */ - if (mode != CCmode && mode != CCRCmode) + if (mode != CCmode) abort (); suffix = fp ? "nbe" : "a"; break; case LT: if (mode == CCNOmode || mode == CCGOCmode) suffix = "s"; - else if (mode == CCmode || mode == CCGCmode || mode == CCRCmode) + else if (mode == CCmode || mode == CCGCmode) suffix = "l"; else abort (); @@ -3140,33 +3135,26 @@ put_condition_code (code, mode, reverse, fp, file) case GE: if (mode == CCNOmode || mode == CCGOCmode) suffix = "ns"; - else if (mode == CCmode || mode == CCGCmode || mode == CCRCmode) + else if (mode == CCmode || mode == CCGCmode) suffix = "ge"; else abort (); break; case GEU: /* ??? As above. */ - if (mode != CCmode && mode != CCRCmode) + if (mode != CCmode) abort (); - if (mode == CCRCmode) - suffix = "be"; - else - suffix = fp ? "nb" : "ae"; + suffix = fp ? "nb" : "ae"; break; case LE: - if (mode != CCmode && mode != CCGCmode && mode != CCNOmode - && mode != CCRCmode) + if (mode != CCmode && mode != CCGCmode && mode != CCNOmode) abort (); suffix = "le"; break; case LEU: if (mode != CCmode) abort (); - if (mode == CCRCmode) - suffix = fp ? "nb" : "ae"; - else - suffix = "be"; + suffix = "be"; break; case UNORDERED: suffix = "p"; @@ -4594,13 +4582,6 @@ ix86_match_ccmode (insn, req_mode) return 0; break; case CCmode: - if (req_mode == CCRCmode) - return 0; - goto no_carry; - case CCRCmode: - if (req_mode == CCmode) - return 0; - no_carry: if (req_mode == CCGCmode) return 0; /* FALLTHRU */ @@ -4732,18 +4713,15 @@ ix86_cc_mode (code, op0, op1) case NE: /* ZF!=0 */ return CCZmode; /* Codes needing carry flag. */ - case LTU: /* CF=1 */ - case LEU: /* CF=1 | ZF=1 */ - return CCmode; case GEU: /* CF=0 */ case GTU: /* CF=0 & ZF=0 */ - if (GET_CODE (op1) == NEG) - return CCRCmode; + case LTU: /* CF=1 */ + case LEU: /* CF=1 | ZF=1 */ return CCmode; /* Codes possibly doable only with sign flag when comparing against zero. */ case GE: /* SF=OF or SF=0 */ - case LT: /* SF<>OF or SF=0 */ + case LT: /* SF<>OF or SF=1 */ if (op1 == const0_rtx) return CCGOCmode; else @@ -6197,8 +6175,8 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch) /* Avoid branch in fixing the byte. */ tmpreg = gen_lowpart (QImode, tmpreg); - emit_insn (gen_addqi3_ccrc (tmpreg, tmpreg, tmpreg)); - emit_insn (gen_subsi3_carry_rc (out, out, GEN_INT (3))); + emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg)); + emit_insn (gen_subsi3_carry (out, out, GEN_INT (3))); emit_label (end_0_label); } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f0223bc711f..7bc5f582b4e 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2478,8 +2478,8 @@ while (0) equality comparisons are being done. Add CCNO to indicate comparisons against zero that requires - No Overflow. Sign bit test is used instead and thus - can be used to form "a&b>0" type of tests. + Overflow flag to be unset. Sign bit test is used instead and + thus can be used to form "a&b>0" type of tests. Add CCGC to indicate comparisons agains zero that allows unspecified garbage in the Carry flag. This mode is used @@ -2490,14 +2490,10 @@ while (0) mode is used to simulate comparisons of (a-b) and (a+b) against zero using sub/cmp/add operations. - Add CCZ to indicate that only the Zero flag is valid. - - Add CCRC to indicate that carry flag is valid, but reversed. -*/ + Add CCZ to indicate that only the Zero flag is valid. */ #define EXTRA_CC_MODES \ CC(CCGCmode, "CCGC") \ - CC(CCRCmode, "CCRC") \ CC(CCGOCmode, "CCGOC") \ CC(CCNOmode, "CCNO") \ CC(CCZmode, "CCZ") \ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1aea39e1d84..9f662a390fe 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -71,6 +71,7 @@ ;; 9 This is an `fnstsw' operation. ;; 10 This is a `sahf' operation. ;; 11 This is a `fstcw' operation +;; 12 This is behaviour of add when setting carry flag. ;; For SSE/MMX support: ;; 30 This is `fix', guaranteed to be truncating. @@ -3738,11 +3739,10 @@ (match_operand:DI 2 "general_operand" ""))) (clobber (reg:CC 17))] "reload_completed" - [(parallel [(set (reg:CCRC 17) - (compare:CCRC (match_dup 1) (neg:SI (match_dup 2)))) + [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12)) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (parallel [(set (match_dup 3) - (plus:SI (plus:SI (gtu:SI (reg:CCRC 17) (const_int 0)) + (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) (match_dup 4)) (match_dup 5))) (clobber (reg:CC 17))])] @@ -3763,18 +3763,25 @@ (set_attr "mode" "SI") (set_attr "ppro_uops" "few")]) -(define_insn "*addsi3_carry_rc" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") - (plus:SI (plus:SI (gtu:SI (reg:CCRC 17) (const_int 0)) - (match_operand:SI 1 "nonimmediate_operand" "%0,0")) - (match_operand:SI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] +(define_insn "*addsi3_cc" + [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") + (match_operand:SI 2 "general_operand" "ri,rm")] 12)) + (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") + (plus:SI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, SImode, operands)" - "adc{l}\\t{%2, %0|%0, %2}" + "add{l}\\t{%2, %0|%0, %2}" [(set_attr "type" "alu") - (set_attr "pent_pair" "pu") - (set_attr "mode" "SI") - (set_attr "ppro_uops" "few")]) + (set_attr "mode" "SI")]) + +(define_insn "addqi3_cc" + [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qi,qm")] 12)) + (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") + (plus:QI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (PLUS, QImode, operands)" + "add{b}\\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) (define_expand "addsi3" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") @@ -4020,10 +4027,10 @@ (define_insn "*addsi_3" [(set (reg 17) - (compare (match_operand:SI 1 "nonimmediate_operand" "%0") - (neg:SI (match_operand:SI 2 "general_operand" "rmni")))) + (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) + (match_operand:SI 1 "nonimmediate_operand" "%0"))) (clobber (match_scratch:SI 0 "=r"))] - "ix86_match_ccmode (insn, CCGCmode) + "ix86_match_ccmode (insn, CCZmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) /* Current assemblers are broken and do not allow @GOTOFF in ought but a memory context. */ @@ -4064,36 +4071,53 @@ (const_string "alu"))) (set_attr "mode" "SI")]) +; For comparisons agains 1, -1 and 128, we may generate better code +; by converting cmp to add, inc or dec as done by peephole2. This pattern +; is matched then. We can't accept general immediate, because for +; case of overflows, the result is messed up. +; This pattern also don't hold of 0x80000000, since the value overflows +; when negated. +; Also carry flag is reversed compared to cmp, so this converison is valid +; only for comparisons not depending on it. (define_insn "*addsi_4" [(set (reg 17) - (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0") - (neg:SI (match_operand:SI 2 "general_operand" "rmni,rni")))) - (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") - (plus:SI (match_dup 1) (match_dup 2)))] - "ix86_binary_operator_ok (PLUS, SImode, operands) - && ix86_match_ccmode (insn, CCRCmode) - /* Current assemblers are broken and do not allow @GOTOFF in - ought but a memory context. */ - && ! pic_symbolic_operand (operands[2], VOIDmode)" - "add{l}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "mode" "SI")]) + (compare (match_operand:SI 1 "nonimmediate_operand" "0") + (match_operand:SI 2 "const_int_operand" "n"))) + (clobber (match_scratch:SI 0 "=rm"))] + "ix86_match_ccmode (insn, CCGCmode) + && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000" + "* +{ + switch (get_attr_type (insn)) + { + case TYPE_INCDEC: + if (operands[2] == constm1_rtx) + return \"inc{l}\\t%0\"; + else if (operands[2] == const1_rtx) + return \"dec{l}\\t%0\"; + else + abort(); -(define_insn "*addsi_5" - [(set (reg 17) - (compare (match_operand:SI 1 "nonimmediate_operand" "%0") - (neg:SI (match_operand:SI 2 "general_operand" "rmni")))) - (clobber (match_scratch:SI 0 "=r"))] - "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) - && ix86_match_ccmode (insn, CCRCmode) - /* Current assemblers are broken and do not allow @GOTOFF in - ought but a memory context. */ - && ! pic_symbolic_operand (operands[2], VOIDmode)" - "add{l}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") + default: + if (! rtx_equal_p (operands[0], operands[1])) + abort (); + /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. + Exceptions: -128 encodes smaller than 128, so swap sign and op. */ + if ((INTVAL (operands[2]) == -128 + || (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) != 128))) + return \"sub{l}\\t{%2, %0|%0, %2}\"; + operands[2] = GEN_INT (-INTVAL (operands[2])); + return \"add{l}\\t{%2, %0|%0, %2}\"; + } +}" + [(set (attr "type") + (if_then_else (match_operand:SI 2 "incdec_operand" "") + (const_string "incdec") + (const_string "alu"))) (set_attr "mode" "SI")]) -(define_insn "*addsi_6" +(define_insn "*addsi_5" [(set (reg 17) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") @@ -4282,10 +4306,10 @@ (define_insn "*addhi_3" [(set (reg 17) - (compare (match_operand:HI 1 "nonimmediate_operand" "%0") - (neg:HI (match_operand:HI 2 "general_operand" "rmni")))) + (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni")) + (match_operand:HI 1 "nonimmediate_operand" "%0"))) (clobber (match_scratch:HI 0 "=r"))] - "ix86_match_ccmode (insn, CCGCmode) + "ix86_match_ccmode (insn, CCZmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* { @@ -4320,30 +4344,49 @@ (const_string "alu"))) (set_attr "mode" "HI")]) +; See comments above addsi_3_imm for details. (define_insn "*addhi_4" [(set (reg 17) - (compare (match_operand:HI 1 "nonimmediate_operand" "%0,0") - (neg:HI (match_operand:HI 2 "general_operand" "rmni,rni")))) - (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") - (plus:HI (match_dup 1) (match_dup 2)))] - "ix86_match_ccmode (insn, CCRCmode) - && ix86_binary_operator_ok (PLUS, HImode, operands)" - "add{w}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "mode" "HI")]) + (compare (match_operand:HI 1 "nonimmediate_operand" "0") + (match_operand:HI 2 "const_int_operand" "n"))) + (clobber (match_scratch:HI 0 "=rm"))] + "ix86_match_ccmode (insn, CCGCmode) + && (INTVAL (operands[2]) & 0xffff) != 0x8000" + "* +{ + switch (get_attr_type (insn)) + { + case TYPE_INCDEC: + if (operands[2] == constm1_rtx + || (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 65535)) + return \"inc{w}\\t%0\"; + else if (operands[2] == const1_rtx) + return \"dec{w}\\t%0\"; + else + abort(); + + default: + if (! rtx_equal_p (operands[0], operands[1])) + abort (); + /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. + Exceptions: -128 encodes smaller than 128, so swap sign and op. */ + if ((INTVAL (operands[2]) == -128 + || (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) != 128))) + return \"sub{w}\\t{%2, %0|%0, %2}\"; + operands[2] = GEN_INT (-INTVAL (operands[2])); + return \"add{w}\\t{%2, %0|%0, %2}\"; + } +}" + [(set (attr "type") + (if_then_else (match_operand:HI 2 "incdec_operand" "") + (const_string "incdec") + (const_string "alu"))) + (set_attr "mode" "SI")]) -(define_insn "*addhi_5" - [(set (reg 17) - (compare (match_operand:HI 1 "nonimmediate_operand" "%0") - (neg:HI (match_operand:HI 2 "general_operand" "rmni")))) - (clobber (match_scratch:HI 0 "=r"))] - "ix86_match_ccmode (insn, CCRCmode) - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "add{w}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "mode" "HI")]) -(define_insn "*addhi_6" +(define_insn "*addhi_5" [(set (reg 17) (compare (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0") @@ -4534,10 +4577,10 @@ (define_insn "*addqi_3" [(set (reg 17) - (compare (match_operand:QI 1 "nonimmediate_operand" "%0") - (neg:QI (match_operand:QI 2 "general_operand" "qmni")))) - (clobber (match_scratch:QI 0 "=r"))] - "ix86_match_ccmode (insn, CCGCmode) + (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni")) + (match_operand:QI 1 "nonimmediate_operand" "%0"))) + (clobber (match_scratch:QI 0 "=q"))] + "ix86_match_ccmode (insn, CCZmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* { @@ -4569,45 +4612,53 @@ (const_string "alu"))) (set_attr "mode" "QI")]) +; See comments above addsi_3_imm for details. (define_insn "*addqi_4" [(set (reg 17) - (compare (match_operand:QI 1 "nonimmediate_operand" "%0,0") - (neg:QI (match_operand:QI 2 "general_operand" "qmni,qni")))) - (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") - (plus:QI (match_dup 1) (match_dup 2)))] - "ix86_match_ccmode (insn, CCRCmode) - && ix86_binary_operator_ok (PLUS, QImode, operands)" - "add{b}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") + (compare (match_operand:QI 1 "nonimmediate_operand" "0") + (match_operand:QI 2 "const_int_operand" "n"))) + (clobber (match_scratch:QI 0 "=qm"))] + "ix86_match_ccmode (insn, CCGCmode) + && (INTVAL (operands[2]) & 0xff) != 0x80" + "* +{ + switch (get_attr_type (insn)) + { + case TYPE_INCDEC: + if (operands[2] == constm1_rtx + || (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 255)) + return \"inc{b}\\t%0\"; + else if (operands[2] == const1_rtx) + return \"dec{b}\\t%0\"; + else + abort(); + + default: + if (! rtx_equal_p (operands[0], operands[1])) + abort (); + if (INTVAL (operands[2]) < 0) + { + operands[2] = GEN_INT (-INTVAL (operands[2])); + return \"add{b}\\t{%2, %0|%0, %2}\"; + } + return \"sub{b}\\t{%2, %0|%0, %2}\"; + } +}" + [(set (attr "type") + (if_then_else (match_operand:HI 2 "incdec_operand" "") + (const_string "incdec") + (const_string "alu"))) (set_attr "mode" "QI")]) -(define_expand "addqi3_ccrc" - [(parallel [ - (set (reg:CCRC 17) - (compare:CCRC (match_operand:QI 1 "nonimmediate_operand" "") - (neg:QI (match_operand:QI 2 "general_operand" "")))) - (clobber (match_scratch:QI 0 ""))])] - "" - "") (define_insn "*addqi_5" - [(set (reg 17) - (compare (match_operand:QI 1 "nonimmediate_operand" "%0") - (neg:QI (match_operand:QI 2 "general_operand" "qmni")))) - (clobber (match_scratch:QI 0 "=r"))] - "ix86_match_ccmode (insn, CCRCmode) - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "add{b}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "mode" "QI")]) - -(define_insn "*addqi_6" [(set (reg 17) (compare (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "general_operand" "qmni")) (const_int 0))) - (clobber (match_scratch:QI 0 "=r"))] + (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCGOCmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* @@ -4748,7 +4799,7 @@ split_di (operands+1, 1, operands+1, operands+4); split_di (operands+2, 1, operands+2, operands+5);") -(define_insn "*subsi3_carry" +(define_insn "subsi3_carry" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) @@ -4761,19 +4812,6 @@ (set_attr "ppro_uops" "few") (set_attr "mode" "SI")]) -(define_insn "subsi3_carry_rc" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") - (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") - (plus:SI (gtu:SI (reg:CCRC 17) (const_int 0)) - (match_operand:SI 2 "general_operand" "ri,rm")))) - (clobber (reg:CC 17))] - "ix86_binary_operator_ok (MINUS, SImode, operands)" - "sbb{l}\\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "pent_pair" "pu") - (set_attr "ppro_uops" "few") - (set_attr "mode" "SI")]) - (define_expand "subsi3" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") @@ -5933,7 +5971,7 @@ (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "general_operand" "qim")) (const_int 0))) - (clobber (match_scratch:QI 0 "=r"))] + (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCNOmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "or{b}\\t{%2, %0|%0, %2}" @@ -6092,7 +6130,7 @@ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "general_operand" "qim")) (const_int 0))) - (clobber (match_scratch:QI 0 "=r"))] + (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCNOmode) && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "xor{b}\\t{%2, %0|%0, %2}" @@ -6169,7 +6207,7 @@ (set (match_dup 0) (neg:SI (match_dup 2)))]) (parallel [(set (match_dup 1) - (plus:SI (plus:SI (gtu:SI (reg:CCRC 17) (const_int 0)) + (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) (match_dup 3)) (const_int 0))) (clobber (reg:CC 17))]) @@ -10603,22 +10641,6 @@ (set_attr "mode" "SI") (set_attr "length_immediate" "0")]) -(define_insn "x86_movsicc_0_m1_rc" - [(set (match_operand:SI 0 "register_operand" "=r") - (if_then_else:SI (gtu (reg:CCRC 17) (const_int 0)) - (const_int -1) - (const_int 0))) - (clobber (reg:CC 17))] - "" - "sbb{l}\\t%0, %0" - ; Since we don't have the proper number of operands for an alu insn, - ; fill in all the blanks. - [(set_attr "type" "alu") - (set_attr "memory" "none") - (set_attr "imm_disp" "false") - (set_attr "mode" "SI") - (set_attr "length_immediate" "0")]) - (define_insn "*movsicc_noc" [(set (match_operand:SI 0 "register_operand" "=r,r") (if_then_else:SI (match_operator 1 "ix86_comparison_operator" @@ -11457,9 +11479,9 @@ && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(parallel [(set (reg:CCGC 17) (compare:CCGC (match_dup 0) - (neg:SI (match_dup 1)))) + (match_dup 1))) (clobber (match_dup 0))])] - "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;") + "") (define_peephole2 [(set (reg 17) @@ -11469,9 +11491,9 @@ && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(parallel [(set (reg:CCGC 17) (compare:CCGC (match_dup 0) - (neg:HI (match_dup 1)))) + (match_dup 1))) (clobber (match_dup 0))])] - "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;") + "") (define_peephole2 [(set (reg 17) @@ -11481,20 +11503,20 @@ && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(parallel [(set (reg:CCGC 17) (compare:CCGC (match_dup 0) - (neg:QI (match_dup 1)))) + (match_dup 1))) (clobber (match_dup 0))])] - "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;") + "") ;; Convert compares with 128 to shorter add -128 (define_peephole2 [(set (reg 17) (compare (match_operand:SI 0 "register_operand" "") (const_int 128)))] - "ix86_match_ccmode (insn, CCRCmode) + "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCRC 17) - (compare:CCRC (match_dup 0) - (neg:SI (const_int -128)))) + [(parallel [(set (reg:CCGC 17) + (compare:CCGC (match_dup 0) + (const_int 128))) (clobber (match_dup 0))])] "") @@ -11502,11 +11524,11 @@ [(set (reg 17) (compare (match_operand:HI 0 "register_operand" "") (const_int 128)))] - "ix86_match_ccmode (insn, CCRCmode) + "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCRC 17) - (compare:CCRC (match_dup 0) - (neg:HI (const_int -128)))) + [(parallel [(set (reg:CCGC 17) + (compare:CCGC (match_dup 0) + (const_int 128))) (clobber (match_dup 0))])] "") -- 2.30.2