From 7e0ce3cff91c75b71d4c65df183967c1dfe40793 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 24 Sep 2022 10:25:42 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 2 -- 1 file changed, 2 deletions(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 70ab38d9b..10b0ebac6 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -163,8 +163,6 @@ into a type of `cmp`. The CR is stored (and the CR.eq bit tested against the `inv` field). If the CR.eq bit is equal to `inv` then the Vector is truncated and the loop ends. -Note that when RC1=1 the result elements are never stored, only the CR -Fields. VLi is only available as an option when `Rc=0` (or for instructions which do not have Rc). When set, the current element is always -- 2.30.2