From 7e0d1d92d85dd47cffd15edf150c2b8fe3bf87ad Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 19 Dec 2020 17:28:25 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 9d0950161..bbb90105d 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -103,8 +103,7 @@ Some examples on different operation widths: 0 1 2 3 4 description ------------------ - 0 0 0 0 0 nothing - 0 0 1 sz dz pred zeroing + 0 0 M sz dz reduce mode (M=1) 0 1 inv CR-bit Rc=1: ffirst CR sel 0 1 inv sz dz Rc=0: ffirst z/nonz 1 0 N sz dz sat mode: N=0/1 u/s @@ -116,6 +115,7 @@ Mode types: * **sz dz predicate zeroing** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. * **ffirst** or data-dependent fail-on-first: see separate section. * **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. +* **reduce mode**. when M=1 a mapreduce is performed. the result is a scalar. a vector however is required, as it may be used to store intermediary computations. the result is in the first element with a nonzero predicate bit. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). # Notes about rounding, clamp and saturate -- 2.30.2