From 7e0dd37616e39fcc8f1175860186285aed550519 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 22 Jan 2019 09:08:35 +0100 Subject: [PATCH] soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case With ECC configurations, native port data_width is not necessarily a power of 2. --- litex/soc/integration/soc_sdram.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 432de0b2..5a80256d 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -1,3 +1,5 @@ +from math import log2 + from migen import * from migen.genlib.record import * @@ -76,7 +78,9 @@ class SoCSDRAM(SoCCore): if self.l2_size: port = self.sdram.crossbar.get_port() - l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.dw)) + port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2 + l2_size = 2**int(log2(self.l2_size)) # Round to nearest power of 2 + l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... from litex.build.xilinx.vivado import XilinxVivadoToolchain -- 2.30.2