From 7e1c98bc87e9f6279342319061d3f3afd0fe514f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 19 Dec 2020 15:31:01 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 4d74d1fff..e89ad5e94 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -10,10 +10,10 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]] # Format -| 0..5 |6..10|11..15|16.20|21.22.23.24..25|26.....30|31| name | -|------|-----|------|-----|---------------|---------|--|---------| -| 19 | RT | RA | | XO[0:4] | XO[5:9] |Rc| XL-Form | -| 19 | RT | RA |imm | imm // vs ms | NNNNN |Rc| setvl | +| 0.5|6.10|11.15|16.20|21.....24..25|26.....30|31| name | +|----|----|-----|-----|-------------|---------|--|---------| +| 19 | RT | RA | | XO[0:4] | XO[5:9] |Rc| XL-Form | +| 19 | RT | RA |imm | i // vs ms | NNNNN |Rc| setvl | Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero. Setting bit 22 causes an illegal exception. -- 2.30.2