From 7e2bc00c0a020052b8bf18290e4b2cf00454fc07 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 28 Nov 2012 23:18:53 +0100
Subject: [PATCH] Remove Constant

---
 milkymist/asmicon/bankmachine.py |  2 +-
 milkymist/asmicon/multiplexer.py |  2 +-
 milkymist/uart/__init__.py       |  4 ++--
 top.py                           | 13 ++++++-------
 4 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py
index a2f37a4f..2806f046 100644
--- a/milkymist/asmicon/bankmachine.py
+++ b/milkymist/asmicon/bankmachine.py
@@ -31,7 +31,7 @@ class _AddressSlicer:
 		if isinstance(address, int):
 			return (address & (2**self._b1 - 1)) << self.address_align
 		else:
-			return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
+			return Cat(Replicate(0, self.address_align), address[:self._b1])
 
 class _Selector:
 	def __init__(self, slicer, bankn, slots):
diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index ac4b2265..f8effcaf 100644
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -71,7 +71,7 @@ class _Steerer:
 		sync = []
 		def stb_and(cmd, attr):
 			if not hasattr(cmd, "stb"):
-				return Constant(0)
+				return 0
 			else:
 				return cmd.stb & getattr(cmd, attr)
 		for phase, sel in zip(self.dfi.phases, self.sel):
diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index e59a2b79..0dfa1dd3 100644
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -21,7 +21,7 @@ class UART:
 		enable16 = Signal()
 		enable16_counter = Signal(BV(16))
 		comb = [
-			enable16.eq(enable16_counter == Constant(0, BV(16)))
+			enable16.eq(enable16_counter == 0)
 		]
 		sync = [
 			enable16_counter.eq(enable16_counter - 1),
@@ -43,7 +43,7 @@ class UART:
 				self.tx.eq(0)
 			).Elif(enable16 & tx_busy,
 				tx_count16.eq(tx_count16 + 1),
-				If(tx_count16 == Constant(0, BV(4)),
+				If(tx_count16 == 0,
 					tx_bitcount.eq(tx_bitcount + 1),
 					If(tx_bitcount == 8,
 						self.tx.eq(1)
diff --git a/top.py b/top.py
index 16bc9122..f29f24af 100644
--- a/top.py
+++ b/top.py
@@ -97,14 +97,13 @@ def get():
 			cpu0.ibus,
 			cpu0.dbus
 		], [
-			(binc("000"), norflash0.bus),
-			(binc("001"), sram0.bus),
-			(binc("011"), minimac0.membus),
-			(binc("10"), wishbone2asmi0.wishbone),
-			(binc("11"), wishbone2csr0.wishbone)
+			(lambda a: a[26:29] == 0, norflash0.bus),
+			(lambda a: a[26:29] == 1, sram0.bus),
+			(lambda a: a[26:29] == 3, minimac0.membus),
+			(lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
+			(lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
 		],
-		register=True,
-		offset=1)
+		register=True)
 	
 	#
 	# CSR
-- 
2.30.2