From 7e391ba90438ba1c20c29863d1556cb6bfd1ea29 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 26 Sep 2017 09:19:56 +0300
Subject: [PATCH] enable $bits() and $size() functions only when the
 SystemVerilog flag is enabled for read_verilog

---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 0cde34dc5..5b7e48361 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:;
 				goto apply_newNode;
 			}
 
-			if (str == "\\$size" || str == "\\$bits")
+			if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits"))
 			{
 				if (children.size() != 1)
 					log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-- 
2.30.2