From 7e73ff87c0255a8e0498a47991b640cdece35928 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 23 Oct 2016 16:09:58 +0200 Subject: [PATCH] gallium/radeon: remove unnecessary fields from radeon_surf_level MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/r600/evergreen_state.c | 8 ++++---- src/gallium/drivers/r600/r600_state.c | 8 ++++---- src/gallium/drivers/radeon/r600_texture.c | 10 ++++------ src/gallium/drivers/radeon/radeon_winsys.h | 4 ---- src/gallium/drivers/radeonsi/si_dma.c | 8 ++++---- src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 7 ------- src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 8 -------- 7 files changed, 16 insertions(+), 37 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 6344c832b29..c1379642c08 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -3381,7 +3381,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rsrc->surface.level[src_level].npix_y; + height = u_minify(rsrc->resource.b.b.height0, src_level); detile = 1; x = src_x; y = src_y; @@ -3406,7 +3406,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rdst->surface.level[dst_level].npix_y; + height = u_minify(rdst->resource.b.b.height0, dst_level); detile = 0; x = dst_x; y = dst_y; @@ -3494,8 +3494,8 @@ static void evergreen_dma_copy(struct pipe_context *ctx, bpp = rdst->surface.bpe; dst_pitch = rdst->surface.level[dst_level].pitch_bytes; src_pitch = rsrc->surface.level[src_level].pitch_bytes; - src_w = rsrc->surface.level[src_level].npix_x; - dst_w = rdst->surface.level[dst_level].npix_x; + src_w = u_minify(rsrc->resource.b.b.width0, src_level); + dst_w = u_minify(rdst->resource.b.b.width0, dst_level); copy_height = src_box->height / rsrc->surface.blk_h; dst_mode = rdst->surface.level[dst_level].mode; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 4a94a1902ca..319db63b2a0 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -2857,7 +2857,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rsrc->surface.level[src_level].npix_y; + height = u_minify(rsrc->resource.b.b.height0, src_level); detile = 1; x = src_x; y = src_y; @@ -2876,7 +2876,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rdst->surface.level[dst_level].npix_y; + height = u_minify(rdst->resource.b.b.height0, dst_level); detile = 0; x = dst_x; y = dst_y; @@ -2964,8 +2964,8 @@ static void r600_dma_copy(struct pipe_context *ctx, bpp = rdst->surface.bpe; dst_pitch = rdst->surface.level[dst_level].pitch_bytes; src_pitch = rsrc->surface.level[src_level].pitch_bytes; - src_w = rsrc->surface.level[src_level].npix_x; - dst_w = rdst->surface.level[dst_level].npix_x; + src_w = u_minify(rsrc->resource.b.b.width0, src_level); + dst_w = u_minify(rdst->resource.b.b.width0, dst_level); copy_height = src_box->height / rsrc->surface.blk_h; dst_mode = rdst->surface.level[dst_level].mode; diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index c9c87c7dbb0..74977ea60fb 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -816,8 +816,8 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen, /* HW bug on R6xx. */ if (rscreen->chip_class == R600 && - (rtex->surface.level[0].npix_x > 7680 || - rtex->surface.level[0].npix_y > 7680)) + (rtex->resource.b.b.width0 > 7680 || + rtex->resource.b.b.height0 > 7680)) return 0; /* HTILE is broken with 1D tiling on old kernels and CIK. */ @@ -973,7 +973,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) for (i = 0; i <= rtex->resource.b.b.last_level; i++) fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", " "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "nblk_z=%u, pitch_bytes=%u, mode=%u\n", + "pitch_bytes=%u, mode=%u\n", i, rtex->surface.level[i].offset, rtex->surface.level[i].slice_size, u_minify(rtex->resource.b.b.width0, i), @@ -981,7 +981,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) u_minify(rtex->resource.b.b.depth0, i), rtex->surface.level[i].nblk_x, rtex->surface.level[i].nblk_y, - rtex->surface.level[i].nblk_z, rtex->surface.level[i].pitch_bytes, rtex->surface.level[i].mode); @@ -992,7 +991,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", " "slice_size=%"PRIu64", npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "nblk_z=%u, pitch_bytes=%u, mode=%u\n", + "pitch_bytes=%u, mode=%u\n", i, rtex->surface.stencil_level[i].offset, rtex->surface.stencil_level[i].slice_size, u_minify(rtex->resource.b.b.width0, i), @@ -1000,7 +999,6 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) u_minify(rtex->resource.b.b.depth0, i), rtex->surface.stencil_level[i].nblk_x, rtex->surface.stencil_level[i].nblk_y, - rtex->surface.stencil_level[i].nblk_z, rtex->surface.stencil_level[i].pitch_bytes, rtex->surface.stencil_level[i].mode); } diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 4573efe14ed..a28bac1d8bc 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -280,12 +280,8 @@ struct radeon_surf_level { uint64_t slice_size; uint64_t dcc_offset; uint64_t dcc_fast_clear_size; - uint16_t npix_x; - uint16_t npix_y; - uint16_t npix_z; uint16_t nblk_x; uint16_t nblk_y; - uint16_t nblk_z; uint32_t pitch_bytes; enum radeon_surf_mode mode; bool dcc_enabled; diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 3df52bddc44..6bbb5d647d9 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -234,16 +234,16 @@ static void si_dma_copy(struct pipe_context *ctx, bpp = rdst->surface.bpe; dst_pitch = rdst->surface.level[dst_level].pitch_bytes; src_pitch = rsrc->surface.level[src_level].pitch_bytes; - src_w = rsrc->surface.level[src_level].npix_x; - dst_w = rdst->surface.level[dst_level].npix_x; + src_w = u_minify(rsrc->resource.b.b.width0, src_level); + dst_w = u_minify(rdst->resource.b.b.width0, dst_level); dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w || src_box->width != src_w || - src_box->height != rsrc->surface.level[src_level].npix_y || - src_box->height != rdst->surface.level[dst_level].npix_y || + src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) || + src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) || rsrc->surface.level[src_level].nblk_y != rdst->surface.level[dst_level].nblk_y) { /* FIXME si can do partial blit */ diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 3b4c13b6baf..e6a26188677 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -192,15 +192,8 @@ static int compute_level(struct amdgpu_winsys *ws, surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); surf_level->slice_size = AddrSurfInfoOut->sliceSize; surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe); - surf_level->npix_x = u_minify(tex->width0, level); - surf_level->npix_y = u_minify(tex->height0, level); - surf_level->npix_z = u_minify(tex->depth0, level); surf_level->nblk_x = AddrSurfInfoOut->pitch; surf_level->nblk_y = AddrSurfInfoOut->height; - if (tex->target == PIPE_TEXTURE_3D) - surf_level->nblk_z = AddrSurfInfoOut->depth; - else - surf_level->nblk_z = 1; switch (AddrSurfInfoOut->tileMode) { case ADDR_TM_LINEAR_ALIGNED: diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index 18c68a50ff7..ed614064ce8 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -71,12 +71,8 @@ static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm, { level_drm->offset = level_ws->offset; level_drm->slice_size = level_ws->slice_size; - level_drm->npix_x = level_ws->npix_x; - level_drm->npix_y = level_ws->npix_y; - level_drm->npix_z = level_ws->npix_z; level_drm->nblk_x = level_ws->nblk_x; level_drm->nblk_y = level_ws->nblk_y; - level_drm->nblk_z = level_ws->nblk_z; level_drm->pitch_bytes = level_ws->pitch_bytes; level_drm->mode = level_ws->mode; } @@ -86,12 +82,8 @@ static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws, { level_ws->offset = level_drm->offset; level_ws->slice_size = level_drm->slice_size; - level_ws->npix_x = level_drm->npix_x; - level_ws->npix_y = level_drm->npix_y; - level_ws->npix_z = level_drm->npix_z; level_ws->nblk_x = level_drm->nblk_x; level_ws->nblk_y = level_drm->nblk_y; - level_ws->nblk_z = level_drm->nblk_z; level_ws->pitch_bytes = level_drm->pitch_bytes; level_ws->mode = level_drm->mode; } -- 2.30.2