From 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 18:43:17 -0700
Subject: [PATCH] Trim shiftx_width when upper bits are 1'bx

---
 passes/pmgen/xilinx_srl.pmg | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index 3f4efebe9..d3ba0109f 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -164,6 +164,11 @@ endmatch
 
 code shiftx_width
 	shiftx_width = param(shiftx, \A_WIDTH).as_int();
+	while (shiftx_width > 1) {
+		if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
+			break;
+		--shiftx_width;
+	}
 endcode
 
 match first
@@ -177,7 +182,7 @@ code
 	chain.push_back(first);
 	subpattern(tail);
 finally
-	if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
+	if (GetSize(chain) == shiftx_width)
 		accept;
 	chain.clear();
 endcode
-- 
2.30.2