From 7e9297e8b43f13d7ced8bbeac02819a446f384eb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 12:39:11 +0000 Subject: [PATCH] make firmware and cpu optional for now to get a basic compile --- examples/crg.py | 3 +-- examples/soc.py | 48 ++++++++++++++++++++++++++++-------------------- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/examples/crg.py b/examples/crg.py index 3e3b432..eb3c651 100644 --- a/examples/crg.py +++ b/examples/crg.py @@ -1,8 +1,7 @@ # Copyright (c) 2020 LambdaConcept # Copyright (c) 2021 Luke Kenneth Casson Leighton - -from nmigen import (Elaboratable, Instance, Signal, ClockDomain, +from nmigen import (Module, Elaboratable, Instance, Signal, ClockDomain, ClockSignal, ResetSignal) __ALL__ = ["ECPIX5CRG"] diff --git a/examples/soc.py b/examples/soc.py index 889f241..8e489e1 100644 --- a/examples/soc.py +++ b/examples/soc.py @@ -34,9 +34,9 @@ class DDR3SoC(SoC, Elaboratable): def __init__(self, *, uart_pins, ddr_pins, ddrphy_addr, dramcore_addr, - ddr_addr, + ddr_addr, fw_addr=0x0000_0000, firmware=None, - clk_freq=10e6): + clk_freq=40e6): # set up wishbone bus arbiter and decoder. arbiter routes, # decoder maps local-relative addressed satellites to global addresses @@ -51,20 +51,24 @@ class DDR3SoC(SoC, Elaboratable): if firmware is None: firmware = "firmware/main.bin" - # set up clock request generator, CPU, and interrupt interface + # set up clock request generator self.crg = ECPIX5CRG() - self.cpu = MinervaCPU(reset_address=0) - self._arbiter.add(self.cpu.ibus) # I-Cache Master - self._arbiter.add(self.cpu.dbus) # D-Cache Master. TODO JTAG master - self.intc = GenericInterruptController(width=len(self.cpu.ip)) + + if False: + # set up CPU, and interrupt interface + self.cpu = MinervaCPU(reset_address=0) + self._arbiter.add(self.cpu.ibus) # I-Cache Master + self._arbiter.add(self.cpu.dbus) # D-Cache Master. TODO JTAG master + self.intc = GenericInterruptController(width=len(self.cpu.ip)) # SRAM (but actually a ROM, for firmware), at address 0x0 - self.rom = SRAMPeripheral(size=4096, writable=False) - with open(, "rb") as f: - words = iter(lambda: f.read(self.cpu.data_width // 8), b'') - bios = [int.from_bytes(w, self.cpu.byteorder) for w in words] - self.rom.init = bios - self._decoder.add(self.rom.bus, addr=0) # ROM is at 0x0000_0000 + if fw_addr is not None: + self.rom = SRAMPeripheral(size=4096, writable=False) + with open(firmware, "rb") as f: + words = iter(lambda: f.read(self.cpu.data_width // 8), b'') + bios = [int.from_bytes(w, self.cpu.byteorder) for w in words] + self.rom.init = bios + self._decoder.add(self.rom.bus, addr=fw_addr) # ROM at fw_addr # SRAM (read-writeable BRAM) self.ram = SRAMPeripheral(size=4096) @@ -107,11 +111,13 @@ class DDR3SoC(SoC, Elaboratable): # add the peripherals and clock-reset-generator m.submodules.sysclk = self.crg - m.submodules.rom = self.rom + if hasattr(self, "rom"): + m.submodules.rom = self.rom m.submodules.ram = self.ram m.submodules.uart = self.uart - m.submodules.intc = self.intc - m.submodules.cpu = self.cpu + if False: + m.submodules.intc = self.intc + m.submodules.cpu = self.cpu m.submodules.arbiter = self._arbiter m.submodules.decoder = self._decoder m.submodules.ddrphy = self.ddrphy @@ -122,8 +128,9 @@ class DDR3SoC(SoC, Elaboratable): # to the decoder (addressing wishbone slaves) comb += self._arbiter.bus.connect(self._decoder.bus) - # wire up the CPU interrupts - comb += self.cpu.ip.eq(self.intc.ip) + if False: + # wire up the CPU interrupts + comb += self.cpu.ip.eq(self.intc.ip) return m @@ -138,9 +145,10 @@ if __name__ == "__main__": uart_pins = platform.request("uart", 0) soc = DDR3SoC(ddrphy_addr=0xff000000, # DRAM firmware init base - dramcore_addr=0x40000000, + dramcore_addr=0x80000000, ddr_addr=0x10000000, ddr_pins=ddr_pins, - uart_pins=uart_pins) + uart_pins=uart_pins, + fw_addr=None) platform.build(soc, do_program=True) -- 2.30.2