From 7e938af1154deb5b3bcbbe010a982bcd6dbe5e44 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 25 Apr 2022 17:40:31 +0100
Subject: [PATCH]

---
 openpower/isa/svfixedarith.mdwn | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index bb0c798b2..5bf718bfe 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -15,3 +15,35 @@ Pseudo-code:
 Special Registers Altered:
 
     None
+
+# [DRAFT] Twin Divide Quad Unsigned
+
+XO-Form
+
+* divmod2du RT,RA,RB (OE=0 Rc=0)
+* divmod2du.  RT,RA,RB (OE=0 Rc=1)
+* divmod2duo RT,RA,RB (OE=1 Rc=0)
+* divmod2duo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
+    divisor[0:XLEN-1] <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1]
+    if (divisor = [0]*XLEN) then
+        overflow <- 1
+    else
+        result <- dividend / divisor
+        if RA[XLEN/2:XLEN-1] <u RB[XLEN/2:XLEN-1] then
+            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
+            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+            overflow <- 0
+        else
+            overflow <- 1
+    if overflow = 1 then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+    SO OV OV32                              (if OE=1)
+
-- 
2.30.2