From 7eb2cae95ac9bc8b54656a02996c6e763ca29d71 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 6 Sep 2021 16:22:01 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 6aa54155b..fefe53172 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,7 +129,8 @@ Brief description of fields:
 
 * **sz=1** if predication is enabled and `sz=1` and a predicate
   element bit is zero, `SNZ` will
-  be substituted in place of the CR bit selected by `BI`.
+  be substituted in place of the CR bit selected by `BI`,
+  as the Condition tested.
   Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.
-- 
2.30.2