From 7ebf08db5ea1904ca22e6bb3fd4d8fc2a21b6c7f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 6 Aug 2014 23:51:50 +0800 Subject: [PATCH] mibuild/xilinx: connect CE on reset synchronizer FFs --- mibuild/xilinx_common.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx_common.py index dbd3decd..1d3c5800 100644 --- a/mibuild/xilinx_common.py +++ b/mibuild/xilinx_common.py @@ -72,9 +72,9 @@ class XilinxAsyncResetSynchronizerImpl(Module): rst1 = Signal() self.specials += [ Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, - i_C=cd.clk, o_Q=rst1), + i_CE=1, i_C=cd.clk, o_Q=rst1), Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset, - i_C=cd.clk, o_Q=cd.rst) + i_CE=1, i_C=cd.clk, o_Q=cd.rst) ] class XilinxAsyncResetSynchronizer: -- 2.30.2