From 7ecdcaca4b87378e0bda3c3092072df7cbdf9fd6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Jul 2018 18:40:36 +0200 Subject: [PATCH] soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) --- litex/soc/integration/sdram_init.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/sdram_init.py b/litex/soc/integration/sdram_init.py index 8ca1db00..edd6c0d4 100644 --- a/litex/soc/integration/sdram_init.py +++ b/litex/soc/integration/sdram_init.py @@ -68,7 +68,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{ cl = sdram_phy_settings.cl if sdram_phy_settings.memtype == "SDR": - bl = sdram_phy_settings.nphases + bl = 1 mr = log2_int(bl) + (cl << 4) reset_dll = 1 << 8 @@ -83,7 +83,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{ ] elif sdram_phy_settings.memtype == "DDR": - bl = 2*sdram_phy_settings.nphases + bl = 4 mr = log2_int(bl) + (cl << 4) emr = 0 reset_dll = 1 << 8 @@ -100,7 +100,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{ ] elif sdram_phy_settings.memtype == "LPDDR": - bl = 2*sdram_phy_settings.nphases + bl = 4 mr = log2_int(bl) + (cl << 4) emr = 0 reset_dll = 1 << 8 @@ -117,7 +117,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{ ] elif sdram_phy_settings.memtype == "DDR2": - bl = 2*sdram_phy_settings.nphases + bl = 4 wr = 2 mr = log2_int(bl) + (cl << 4) + (wr << 9) emr = 0 @@ -141,7 +141,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{ ("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0), ] elif sdram_phy_settings.memtype == "DDR3": - bl = 2*sdram_phy_settings.nphases + bl = 8 def format_mr0(bl, cl, wr, dll_reset): bl_to_mr0 = { -- 2.30.2