From 7f14444176e05003580b2562e4da36d9a169d704 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 29 Aug 2021 13:29:02 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index f84257b0e..914595e8d 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -481,7 +481,14 @@ Thus, logically, we may set the following rule: Examples of the former type: -* crand, cror, crnor. These all are 5-bit (BA, BB, BC). +* crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit + to be tested against `inv` is the one selected by `BT` +* mcrf. This has only 3-bit (BF, BFA). In order to select the + bit to be tested, the alternative FFirst encoding must be used. + +This limits sv.mcrf in that it may not use the `VLi` (VL inclusive) +Mode. This is unfortunste but unavoidable due to encoding pressure +on SVP64. # pred-result mode -- 2.30.2