From 7f17ad27bf5c51dbe0c91d1b63a22f9ea4f48e4a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Nov 2023 10:08:43 +0000 Subject: [PATCH] got sv.bc working for pospopcount --- src/openpower/decoder/isa/caller.py | 9 ++++----- .../decoder/isa/test_caller_svp64_pospopcount.py | 6 ++++-- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index c4124c7a..3822e629 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -2273,12 +2273,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): # check if this was an sv.bc* and create an indicator that # this is the last check to be made as a loop. combined with - # the ALL/ANY mode we can early-exit + # the ALL/ANY mode we can early-exit. note that BI (to test) + # is an input so there is no termination if BI is scalar + # (because early-termination is for *output* scalars) if self.is_svp64_mode and ins_name.startswith("sv.bc"): - bc_ctrtest = yield self.dec2.rm_dec.bc_ctrtest - no_in_vec = yield self.dec2.no_in_vec # BI is scalar - no_in_vec &= not bc_ctrtest # allow CTR loop on scalar - end_loop = no_in_vec or srcstep == vl-1 or dststep == vl-1 + end_loop = srcstep == vl-1 or dststep == vl-1 self.namespace['end_loop'] = SelectableInt(end_loop, 1) inp_ca_ov = (self.spr['XER'][XER_bits['CA']].value, diff --git a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py index 2e9a4f07..d20a1359 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py @@ -44,14 +44,16 @@ class PosPopCountTestCase(FHDLTestCase): "setvl. 3,0,2,0,1,1", # load VL bytes (update r4 addr) but compressed (dw=8) "sv.lbzu/pi/dw=8 *16, 1(4)", # should be /lf here as well + # bpermd performs the transpose (which gets us to positional..) + "bpermd 4,4", # branch back if still CTR - "sv.bc/ctr/all 16, *0, -0x18", # CTR mode, reduce VL by CTR + "sv.bc/all 16, *0, -0x1c", # CTR mode, reduce VL by CTR ] ) lst = list(lst) tst_array = [23,19,25,189,76,255,32,191,67,205,0,39,107] - tst_array = [1,2,3,] #4,5,6,7,8,9] #8,9,10,11,12,13] + tst_array = [1,2,3,4] #4,5,6,7,8,9] #8,9,10,11,12,13] initial_regs = [0] * 64 initial_regs[3] = len(tst_array) initial_regs[4] = 16 # load address -- 2.30.2