From 7f4aff514551ea434025d6918cce96923fd7e58f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Dec 2021 16:25:10 +0000 Subject: [PATCH] experimenting with option to shorten MultiCompUnit delays --- src/soc/experiment/compalu_multi.py | 6 +++--- src/soc/fu/compunits/compunits.py | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 13850b70..e0931a03 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -260,7 +260,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.d.sync += src_l.r.eq(reset_r) # dest operand latch (not using issue_i) - m.d.sync += req_l.s.eq(alu_pulsem & self.wrmask) + rw_domain += req_l.s.eq(alu_pulsem & self.wrmask) m.d.sync += req_l.r.eq(reset_w | prev_wr_go) # pass operation to the ALU (sync: plenty time to wait for src reads) @@ -293,9 +293,9 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): data_r = Signal.like(lro, name=name, reset_less=True) wrok.append(ok & self.busy_o) with m.If(alu_pulse): - m.d.sync += data_r.eq(lro) + rw_domain += data_r.eq(lro) with m.If(self.issue_i): - m.d.sync += data_r.eq(0) + rw_domain += data_r.eq(0) drl.append(data_r) # ok, above we collated anything with an "ok" on the output side diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 03c28c42..6c8c6696 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -167,7 +167,8 @@ class FunctionUnitBaseMulti(ReservationStations2): for idx in range(num_rows): alu_name = "alu_%s%d" % (alu_name, idx) palu = self.pseudoalus[idx] - cu = MultiCompUnit(regspec, palu, opsubset, name=alu_name) + cu = MultiCompUnit(regspec, palu, opsubset, name=alu_name, + sync_rw=True) cu.fnunit = self.fnunit cu.fu_muxidx = idx self.cu.append(cu) -- 2.30.2