From 7f58d174c4bffa5488f2b5b2ed6e4cd0e0fdbba4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Apr 2019 05:13:00 +0100 Subject: [PATCH] shuffle imports --- src/add/singlepipe.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index b1e808ae..7d08ccff 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -131,17 +131,15 @@ from nmigen import Signal, Mux, Module, Elaboratable from nmigen.cli import verilog, rtlil -from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered -from nmigen.hdl.ast import ArrayProxy +from nmigen.lib.fifo import SyncFIFOBuffered from nmigen.hdl.rec import Record from queue import Queue import inspect -import nmoperator from iocontrol import (PrevControl, NextControl, Object, RecordObject) -from stageapi import (_spec, StageCls, Stage, - StageChain, StageHelper) +from stageapi import (_spec, StageCls, Stage, StageChain, StageHelper) +import nmoperator class RecordBasedStage(Stage): @@ -729,8 +727,9 @@ class RegisterPipeline(UnbufferedPipeline): class FIFOControl(ControlBase): - """ FIFO Control. Uses SyncFIFO to store data, coincidentally + """ FIFO Control. Uses Queue to store data, coincidentally happens to have same valid/ready signalling as Stage API. + (TODO: remove use of SyncFIFOBuffered) data_i -> fifo.din -> FIFO -> fifo.dout -> data_o """ -- 2.30.2