From 7f5925d57c1405ff40acb2fd40b41ab4f189f7a4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Aug 2005 10:22:31 +0000 Subject: [PATCH] Add color tiling support to miniglx for radeon (Stephane Marchesin + Dave Airlie) --- src/glx/mini/driver.h | 2 + src/glx/mini/example.miniglx.conf | 4 ++ src/glx/mini/miniglx.c | 4 ++ src/mesa/drivers/dri/radeon/server/radeon.h | 2 + .../drivers/dri/radeon/server/radeon_dri.c | 67 ++++++++++++++++++- .../drivers/dri/radeon/server/radeon_reg.h | 14 ++++ 6 files changed, 91 insertions(+), 2 deletions(-) diff --git a/src/glx/mini/driver.h b/src/glx/mini/driver.h index 6ce339d98d4..27402641b73 100644 --- a/src/glx/mini/driver.h +++ b/src/glx/mini/driver.h @@ -68,6 +68,8 @@ typedef struct DRIDriverContextRec { int cpp; int agpmode; int isPCI; + + int colorTiling; /**< \brief color tiling is enabled */ unsigned long FBStart; /**< \brief physical address of the framebuffer */ unsigned long MMIOStart; /**< \brief physical address of the MMIO region */ diff --git a/src/glx/mini/example.miniglx.conf b/src/glx/mini/example.miniglx.conf index 1f39f7958bd..62dd4f65ec4 100644 --- a/src/glx/mini/example.miniglx.conf +++ b/src/glx/mini/example.miniglx.conf @@ -30,3 +30,7 @@ agpmode=1 # Rotated monitor? -- NOTE: only works with subsetted radeon driver! rotateMode=0 + +# Do we want to use color tiling ? +colorTiling=0 + diff --git a/src/glx/mini/miniglx.c b/src/glx/mini/miniglx.c index c3001e97651..1dd21bd1f0e 100644 --- a/src/glx/mini/miniglx.c +++ b/src/glx/mini/miniglx.c @@ -878,6 +878,7 @@ static int __read_config_file( Display *dpy ) dpy->rotateMode = 0; dpy->driverContext.agpmode = 1; dpy->driverContext.isPCI = 0; + dpy->driverContext.colorTiling = 0; fname = getenv("MINIGLX_CONF"); if (!fname) fname = "/etc/miniglx.conf"; @@ -950,6 +951,9 @@ static int __read_config_file( Display *dpy ) else if (strcmp(opt, "isPCI") == 0) { dpy->driverContext.isPCI = atoi(val) ? 1 : 0; } + else if (strcmp(opt, "colorTiling") == 0) { + dpy->driverContext.colorTiling = atoi(val) ? 1 : 0; + } } fclose(file); diff --git a/src/mesa/drivers/dri/radeon/server/radeon.h b/src/mesa/drivers/dri/radeon/server/radeon.h index 7966859078b..b83f87cb231 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon.h +++ b/src/mesa/drivers/dri/radeon/server/radeon.h @@ -173,6 +173,8 @@ typedef struct { unsigned int frontPitchOffset; unsigned int backPitchOffset; unsigned int depthPitchOffset; + + int colorTiling; /**< \brief Enable color tiling */ int irq; /**< \brief IRQ number */ int page_flip_enable; /**< \brief Page Flip enable */ diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c index 78ae30beb22..0373036973e 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c +++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.c @@ -26,6 +26,21 @@ static size_t radeon_drm_page_size; +static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value) +{ + drm_radeon_setparam_t sp; + + memset(&sp, 0, sizeof(sp)); + sp.param = param; + sp.value = value; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) { + return -1; + } + + return 0; +} + /** * \brief Wait for free FIFO entries. * @@ -210,6 +225,8 @@ static int RADEONEngineRestore( const DRIDriverContext *ctx ) OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); /* Initialize and start the CP if required */ @@ -786,6 +803,44 @@ static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) (info->depthOffset >> 10)); return 1; +} + +static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + int width_bytes = ctx->shared.virtualWidth * ctx->cpp; + int bufferSize = ((ctx->shared.virtualHeight * width_bytes + + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + /* Setup color tiling */ + if (info->drmMinor<14) + info->colorTiling=0; + + if (info->colorTiling) + { + + int colorTilingFlag; + drm_radeon_surface_alloc_t front,back; + + RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0); + + /* Setup the surfaces */ + if (info->ChipFamily < CHIP_FAMILY_R200) + colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO; + else + colorTilingFlag=R200_SURF_TILE_COLOR_MACRO; + + front.address = info->frontOffset; + front.size = bufferSize; + front.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front)); + + back.address = info->backOffset; + back.size = bufferSize; + back.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back)); + + } + return 1; } @@ -961,12 +1016,15 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info ) return 0; } + RADEONColorTilingInit(ctx, info); + /* Initialize IRQ */ RADEONDRIIrqInit(ctx, info); /* Initialize kernel gart memory manager */ RADEONDRIAgpHeapInit(ctx, info); + fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis"); fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis"); /* Initialize the SAREA private data structure */ { @@ -990,7 +1048,6 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info ) 0, info->backPitch * ctx->cpp * ctx->shared.virtualHeight ); - /* This is the struct passed to radeon_dri.so for its initialization */ ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec)); ctx->driverClientMsgSize = sizeof(RADEONDRIRec); @@ -1126,6 +1183,8 @@ static int radeonValidateMode( const DRIDriverContext *ctx ) info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; return 1; } @@ -1146,9 +1205,12 @@ static int radeonPostValidateMode( const DRIDriverContext *ctx ) unsigned char *RADEONMMIO = ctx->MMIOAddress; RADEONInfoPtr info = ctx->driverPrivate; + RADEONColorTilingInit( ctx, info); OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); - + return 1; } @@ -1190,6 +1252,7 @@ static int radeonInitFBDev( DRIDriverContext *ctx ) info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; info->ringSize = RADEON_DEFAULT_RING_SIZE; info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP; + info->colorTiling = ctx->colorTiling; info->Chipset = ctx->chipset; diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h index 3b395a76ce8..d290d43cfc9 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h +++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h @@ -1065,6 +1065,20 @@ # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) #define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 #define RADEON_SURFACE1_INFO 0x0b1c -- 2.30.2