From 7f5cad304773ecbfe8b390e0b5d79fe11edb2a6b Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 11 Jul 2018 10:25:40 +0200 Subject: [PATCH] x86/Intel: accept memory operand size specifiers for CET insns --- gas/ChangeLog | 8 ++++++++ gas/testsuite/gas/i386/cet-intel.d | 2 ++ gas/testsuite/gas/i386/cet.d | 2 ++ gas/testsuite/gas/i386/cet.s | 2 ++ gas/testsuite/gas/i386/x86-64-cet-intel.d | 4 ++++ gas/testsuite/gas/i386/x86-64-cet.d | 4 ++++ gas/testsuite/gas/i386/x86-64-cet.s | 4 ++++ opcodes/ChangeLog | 6 ++++++ opcodes/i386-opc.tbl | 8 ++++---- opcodes/i386-tbl.h | 8 ++++---- 10 files changed, 40 insertions(+), 8 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 6de7a6167fe..ddb62358d35 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2018-07-11 Jan Beulich + + * testsuite/gas/i386/cet.s, testsuite/gas/i386/x86-64-cet.s: + Add Intel cases with operand size specifiers. + * testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d, + testsuite/gas/i386/x86-64-cet-intel.d, + testsuite/gas/i386/x86-64-cet.d: Adjust expectations. + 2018-07-11 Jan Beulich * config/tc-i386.c (md_assemble): Also replace an already diff --git a/gas/testsuite/gas/i386/cet-intel.d b/gas/testsuite/gas/i386/cet-intel.d index 79da878511e..96ff807f3eb 100644 --- a/gas/testsuite/gas/i386/cet-intel.d +++ b/gas/testsuite/gas/i386/cet-intel.d @@ -23,7 +23,9 @@ Disassembly of section .text: +[a-f0-9]+: f3 0f 01 ea saveprevssp +[a-f0-9]+: f3 0f 01 2c 01 rstorssp QWORD PTR \[ecx\+eax\*1\] +[a-f0-9]+: 0f 38 f6 02 wrssd \[edx\],eax + +[a-f0-9]+: 0f 38 f6 10 wrssd \[eax\],edx +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx + +[a-f0-9]+: 66 0f 38 f5 3c 2a wrussd \[edx\+ebp\*1\],edi +[a-f0-9]+: f3 0f 01 e8 setssbsy +[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\] +[a-f0-9]+: f3 0f 1e fa endbr64 diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d index 982d40ef97a..0f67716123d 100644 --- a/gas/testsuite/gas/i386/cet.d +++ b/gas/testsuite/gas/i386/cet.d @@ -21,7 +21,9 @@ Disassembly of section .text: +[a-f0-9]+: f3 0f 01 ea saveprevssp +[a-f0-9]+: f3 0f 01 2c 01 rstorssp \(%ecx,%eax,1\) +[a-f0-9]+: 0f 38 f6 02 wrssd %eax,\(%edx\) + +[a-f0-9]+: 0f 38 f6 10 wrssd %edx,\(%eax\) +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\) + +[a-f0-9]+: 66 0f 38 f5 3c 2a wrussd %edi,\(%edx,%ebp,1\) +[a-f0-9]+: f3 0f 01 e8 setssbsy +[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\) +[a-f0-9]+: f3 0f 1e fa endbr64 diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s index f0178a8dd25..730e7d7fd59 100644 --- a/gas/testsuite/gas/i386/cet.s +++ b/gas/testsuite/gas/i386/cet.s @@ -18,7 +18,9 @@ _start: saveprevssp rstorssp QWORD PTR [ecx + eax] wrssd [edx],eax + wrssd dword ptr [eax],edx wrussd [edi + ebp],edx + wrussd dword ptr [edx + ebp],edi setssbsy clrssbsy QWORD PTR [esp + eax] endbr64 diff --git a/gas/testsuite/gas/i386/x86-64-cet-intel.d b/gas/testsuite/gas/i386/x86-64-cet-intel.d index 5e5f4a527bc..7b9a125a125 100644 --- a/gas/testsuite/gas/i386/x86-64-cet-intel.d +++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d @@ -28,9 +28,13 @@ Disassembly of section .text: +[a-f0-9]+: f3 0f 01 ea saveprevssp +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\] +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax + +[a-f0-9]+: 44 0f 38 f6 20 wrssd \[rax\],r12d +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx + +[a-f0-9]+: 4a 0f 38 f6 0c 3a wrssq \[rdx\+r15\*1\],rcx +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax + +[a-f0-9]+: 66 44 0f 38 f5 20 wrussd \[rax\],r12d +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx + +[a-f0-9]+: 66 48 0f 38 f5 1c 01 wrussq \[rcx\+rax\*1\],rbx +[a-f0-9]+: f3 0f 01 e8 setssbsy +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\] +[a-f0-9]+: f3 0f 1e fa endbr64 diff --git a/gas/testsuite/gas/i386/x86-64-cet.d b/gas/testsuite/gas/i386/x86-64-cet.d index af298274a14..27749662aa0 100644 --- a/gas/testsuite/gas/i386/x86-64-cet.d +++ b/gas/testsuite/gas/i386/x86-64-cet.d @@ -27,9 +27,13 @@ Disassembly of section .text: +[a-f0-9]+: f3 0f 01 ea saveprevssp +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp \(%r12\) +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd %eax,\(%r12\) + +[a-f0-9]+: 44 0f 38 f6 20 wrssd %r12d,\(%rax\) +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\) + +[a-f0-9]+: 4a 0f 38 f6 0c 3a wrssq %rcx,\(%rdx,%r15,1\) +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\) + +[a-f0-9]+: 66 44 0f 38 f5 20 wrussd %r12d,\(%rax\) +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\) + +[a-f0-9]+: 66 48 0f 38 f5 1c 01 wrussq %rbx,\(%rcx,%rax,1\) +[a-f0-9]+: f3 0f 01 e8 setssbsy +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\) +[a-f0-9]+: f3 0f 1e fa endbr64 diff --git a/gas/testsuite/gas/i386/x86-64-cet.s b/gas/testsuite/gas/i386/x86-64-cet.s index 33cd4bf3943..54ca839211a 100644 --- a/gas/testsuite/gas/i386/x86-64-cet.s +++ b/gas/testsuite/gas/i386/x86-64-cet.s @@ -24,9 +24,13 @@ _start: saveprevssp rstorssp QWORD PTR [r12] wrssd [r12],eax + wrssd dword ptr [rax],r12d wrssq [rcx+r15],rdx + wrssq qword ptr [rdx+r15],rcx wrussd [r12],eax + wrussd dword ptr [rax],r12d wrussq [rbx+rax],rcx + wrussq qword ptr [rcx+rax],rbx setssbsy clrssbsy QWORD PTR [rsi+r12] endbr64 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a73380ae25f..ec8587cd85a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2018-07-11 Jan Beulich + + * i386-opc.tbl (wrssd, wrussd): Add Dword. + (wrssq, wrussq): Add Qword. + * i386-tbl.h: Re-generate. + 2018-07-11 Jan Beulich * i386-opc.h: Rename OTMax to OTNum. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index fad588ae3ff..2de81b3f795 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -5781,10 +5781,10 @@ rdsspd, 1, 0xf30f1e, 0x1, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf| rdsspq, 1, 0xf30f1e, 0x1, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 } saveprevssp, 0, 0xf30f01ea, None, 3, CpuSHSTK, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } rstorssp, 1, 0xf30f01, 0x5, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } -wrssd, 2, 0x0f38f6, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex } -wrssq, 2, 0x0f38f6, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex } -wrussd, 2, 0x660f38f5, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex } -wrussq, 2, 0x660f38f5, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex } +wrssd, 2, 0x0f38f6, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrssq, 2, 0x0f38f6, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Qword|Unspecified|BaseIndex } +wrussd, 2, 0x660f38f5, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrussq, 2, 0x660f38f5, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Qword|Unspecified|BaseIndex } setssbsy, 0, 0xf30f01e8, None, 3, CpuSHSTK, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } clrssbsy, 1, 0xf30fae, 0x6, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } endbr64, 0, 0xf30f1efa, None, 3, CpuIBT, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d513275debd..4d63d09ca0b 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -92019,7 +92019,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } }, { "wrssq", 2, 0x0f38f6, None, 3, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -92036,7 +92036,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } }, { "wrussd", 2, 0x660f38f5, None, 3, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -92053,7 +92053,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } }, { "wrussq", 2, 0x660f38f5, None, 3, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -92070,7 +92070,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } }, { "setssbsy", 0, 0xf30f01e8, None, 3, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.30.2