From 7f97db1e0d27914ddc71310a1cffe538cb4da5bb Mon Sep 17 00:00:00 2001 From: kajoljain379 Date: Mon, 4 Mar 2019 15:14:41 +0530 Subject: [PATCH] arch-power: Added more Special Purpose Register * Added more special purpose registers. * Added corresponding move functions. Change-Id: I05a6fe75ef9303a0c7071b0260a084b199a8bfbb Signed-off-by: kajoljain379 --- src/arch/power/isa/decoder.isa | 172 ++++++++++++++++++++++---------- src/arch/power/isa/operands.isa | 38 +++++++ src/arch/power/registers.hh | 42 +++++++- 3 files changed, 200 insertions(+), 52 deletions(-) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 1912316d8..239b4e9c0 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -548,82 +548,154 @@ decode PO default Unknown::unknown() { // Generic integer format instructions. format IntOp { 339: decode SPR { - 0x20: mfxer({{ Rt = XER; }}); + 0x004: mftfhar({{ Rt = TFHAR; }}); + 0x008: mfvrsave({{ Rt = VRSAVE; }}); + 0x018: mfsier({{Rt = SIER;}}); + 0x019: mfbescrs({{Rt = BESCRS;}}); + 0x01C: mfppr({{ Rt = PPR; }}); + 0x020: mfxer({{ Rt = XER; }}); + 0x024: mftfiar({{ Rt = TFIAR; }}); + 0x039: mfbescrsu({{Rt = BESCRSU;}}); + 0x044: mftexasr({{ Rt = TEXASR; }}); + 0x05C: mfppr2({{ Rt =PPR32; }}); + 0x078: mfupmc1({{Rt = PMC1;}}); + 0x098: mfupmc2({{Rt = PMC2;}}); + 0x099: mfebbhr({{Rt = EBBHR;}}); + 0x0b8: mfupmc3({{Rt = PMC3;}}); + 0x0b9: mfebbrr({{Rt = EBBRR;}}); + 0x0d8: mfupmc4({{Rt = PMC4;}}); + 0x0d9: mfbescr({{Rt = BESCR;}}); + 0x0f8: mfupmc5({{Rt = PMC5;}}); 0x100: mflr({{ Rt = LR; }}); + 0x104: mfctrl({{ Rt = CTRL; }}); + 0x118: mfupmc6r({{Rt = PMC6;}}); 0x120: mfctr({{ Rt = CTR; }}); 0x188: mftb({{ Rt = TB; }}); + 0x1A8: mftbu({{ Rt = TBU; }}); + 0x1b8: mfsdar({{Rt = SDAR;}}); + 0x1f9: mftar({{Rt = TAR;}}); + 0x204: mftidr({{ Rt = TIDR; }}, [ IsPrivileged ]); + 0x205: mfdpdes({{ Rt = DPDES; }}, [ IsPrivileged ]); + 0x208: mfsprg0({{Rt = SPRG0;}}); + 0x209: mfhsprg0({{Rt = HSPRG0;}}); + 0x20a: mfhmer({{Rt = HMER;}}); + 0x20E: mfptcr({{ Rt = PTCR; }}); + 0x219: mfasdr({{Rt = ASDR;}}); + 0x21a: mfic({{Rt = IC;}}, [ IsPrivileged ]); + 0x21f: mfhir0({{Rt = HIR0;}}); 0x220: mfdscr({{ Rt = DSCR; }}); + 0x228: mfsprg1({{Rt = SPRG1;}}); + 0x229: mfhsprg1({{Rt = HSPRG1;}}); + 0x22a: mfhmeer({{Rt = HMEER;}}); + 0x23a: mfvtb({{Rt = VTB;}}, [ IsPrivileged ]); 0x240: mfdsisr({{ Rt = DSISR; }}); + 0x248: mfsprg2({{Rt = SPRG2;}}); + 0x249: mfhdisr({{Rt = HDSISR;}}); + 0x24a: mfpcr({{Rt = PCR;}}); 0x260: mfdar({{ Rt = DAR; }}); + 0x268: mfsprg3({{Rt = SPRG3;}}); + 0x269: mfhdar({{Rt = HDAR;}}); + 0x285: mfdawr0({{ Rt = DAWR0; }}); + 0x289: mfspurr({{Rt = SPURR;}}, [ IsPrivileged ]); + 0x2a9: mfpurr({{Rt = PURR;}}, [ IsPrivileged ]); 0x2C0: mfdec({{ Rt = DEC; }}); + 0x2c9: mfhdec({{Rt = HDEC;}}); + 0x2fa: mfpsscr({{Rt = PSSCR;}}); + 0x324: mffscr({{Rt = FSCR;}}); + 0x329: mfhrmor({{Rt = HRMOR;}}); 0x340: mfsrr0({{ Rt = SRR0; }}); + 0x345: mfrpr({{ Rt = RPR; }}); + 0x349: mfhssr0({{Rt = HSRR0;}}); 0x360: mfsrr1({{ Rt = SRR1; }}); + 0x365: mfciabr({{ Rt = CIABR; }}); + 0x368: mfcir({{Rt = CIR;}}, [ IsPrivileged ]); + 0x369: mfhssr1({{Rt = HSRR1;}}); 0x380: mfcfar({{ Rt = CFAR; }}); - 0x104: mfctrl({{ Rt = CTRL; }}); - 0x008: mfvrsave({{ Rt = VRSAVE; }}); - 0x1A8: mftbu({{ Rt = TBU; }}); - 0x3E8: mfpvr({{ Rt = PVR; }}); - 0x01C: mfppr({{ Rt = PPR; }}); - 0x05C: mfppr2({{ Rt =PPR32; }}); - 0x20E: mfptcr({{ Rt = PTCR; }}); - 0x208: mfsprg0({{Rt = SPRG0;}}); - 0x228: mfsprg1({{Rt = SPRG1;}}); - 0x248: mfsprg2({{Rt = SPRG2;}}); - 0x268: mfsprg3({{Rt = SPRG3;}}); + 0x3a0: mfamr({{ Rt = AMR; }}, [ IsPrivileged ]); + 0x3a1: mfiamr({{Rt = IAMR;}}); + 0x3a4: mfuamor({{ Rt = UAMOR; }}, [ IsPrivileged ]); + 0x3aa: mfamor({{Rt = AMOR;}}); + 0x3c5: mfhfscr({{Rt = HFSCR;}}); 0x3c9: mflpcr({{Rt = LPCR;}}); - 0x324: mffscr({{Rt = FSCR;}}); - 0x2fa: mfpsscr({{Rt = PSSCR;}}); + 0x3E8: mfpvr({{ Rt = PVR; }}); 0x3e9: mflpidr({{Rt = LPIDR;}}); - 0x3c5: mfhfscr({{Rt = HFSCR;}}); - 0x21f: mfhir0({{Rt = HIR0;}}); - 0x3aa: mfamor({{Rt = AMOR;}}); - 0x3a1: mfiamr({{Rt = IAMR;}}); - 0x369: mfhssr1({{Rt = HSRR1;}}); - 0x349: mfhssr0({{Rt = HSRR0;}}); - 0x2c9: mfhdec({{Rt = HDEC;}}); - 0x24a: mfpcr({{Rt = PCR;}}); + } 467: decode SPR { - 0x20: mtxer({{ XER = Rs; }}); + 0x004: mttfhar({{TFHAR = Rs;}}); + 0x008: mtvrsave({{ VRSAVE = Rs; }}); + 0x019: mtbescrs({{BESCRS = Rs;}}); + 0x01C: mtppr({{ PPR = Rs; }}); + 0x020: mtxer({{ XER = Rs; }}); + 0x024: mttfiar({{TFIAR = Rs;}}); + 0x039: mtbescrsu({{BESCRSU = Rs;}}); + 0x044: mttexasr({{TEXASR = Rs;}}); + 0x05C: mtppr32({{ PPR32 = Rs; }}); + 0x078: mtupmc1({{PMC1 = Rs;}}); + 0x098: mtupmc2({{PMC2 = Rs;}}); + 0x099: mtebbhr({{EBBHR = Rs;}}); + 0x0b8: mtupmc3({{PMC3 = Rs;}}); + 0x0b9: mtebbrr({{EBBRR = Rs;}}); + 0x0d8: mtupmc4({{PMC4 = Rs;}}); + 0x0d9: mtbescr({{BESCR = Rs;}}); + 0x0f8: mtupmc5({{PMC5 = Rs;}}); 0x100: mtlr({{ LR = Rs; }}); + 0x118: mtupmc6({{PMC6 = Rs;}}); 0x120: mtctr({{ CTR = Rs; }}); - 0x390: mttbl({{ TBL = Rs; }}); + 0x1A8: mttbu({{ TBU = Rs; }}); + 0x1f9: mttar({{TAR = Rs;}}); + 0x201: mtpidr({{PIDR = Rs;}}); + 0x204: mttidr({{TIDR = Rs;}}, [ IsPrivileged ]); + 0x205: mtdpdes({{DPDES = Rs;}}); + 0x208: mtsprg0({{SPRG0 = Rs;}}); + 0x209: mthsprg0({{HSPRG0 = Rs;}}); + 0x20a: mthmer({{HMER = Rs;}}); + 0x20E: mtptcr({{ PTCR = Rs; }}); + 0x219: mtasdr({{ASDR = Rs;}}); + 0x21a: mtic({{IC = Rs;}}); + 0x21f: mthir0({{HIR0 = Rs;}}); 0x220: mtdscr({{ DSCR = Rs; }}); + 0x228: mtsprg1({{SPRG1 = Rs;}}); + 0x229: mthsprg1({{HSPRG1 = Rs;}}); + 0x22a: mthmeer({{HMEER = Rs;}}); + 0x238: mtmmcr2({{MMCR2 = Rs;}}); + 0x23a: mtvtb({{VTB = Rs;}}); 0x240: mtdsisr({{ DSISR = Rs; }}); + 0x248: mtsprg2({{SPRG2 = Rs;}}); + 0x249: mthdisr({{HDSISR = Rs;}}); + 0x24a: mtpcr({{PCR = Rs;}}); + 0x258: mtmmcra({{MMCRA = Rs;}}); 0x260: mtdar({{ DAR = Rs; }}); + 0x268: mtsprg3({{SPRG3 = Rs;}}); + 0x269: mthdar({{HDAR = Rs;}}); + 0x27a: mtmmcrc({{MMCRC = Rs;}}); + 0x285: mtdawr0({{DAWR0 = Rs;}}); + 0x289: mtspurr({{SPURR = Rs;}}); + 0x2a9: mtpurr({{PURR = Rs;}}); 0x2C0: mtdec({{ DEC = Rs; }}); + 0x2c9: mthdec({{HDEC = Rs;}}); + 0x2fa: mtpsscr({{PSSCR = Rs;}}); + 0x304: mtctrl({{ CTRL = Rs; }}); + 0x324: mtfscr({{FSCR = Rs;}}); + 0x329: mthrmor({{HRMOR = Rs;}}); 0x340: mtsrr0({{ SRR0 = Rs; }}); + 0x345: mtrpr({{RPR = Rs;}}); + 0x349: mthssr0({{HSRR0 = Rs;}}); 0x360: mtsrr1({{ SRR1 = Rs; }}); + 0x365: mtciabr({{CIABR = Rs;}}); + 0x369: mthssr1({{HSRR1 = Rs;}}); + 0x378: mtmmcr0({{MMCR0 = Rs;}}); 0x380: mtcfar({{ CFAR = Rs; }}); - 0x304: mtctrl({{ CTRL = Rs; }}); - 0x008: mtvrsave({{ VRSAVE = Rs; }}); - 0x1A8: mttbu({{ TBU = Rs; }}); - 0x01C: mtppr({{ PPR = Rs; }}); - 0x05C: mtppr32({{ PPR32 = Rs; }}); - 0x20E: mtptcr({{ PTCR = Rs; }}); - 0x208: mtsprg0({{SPRG0 = Rs;}}); - 0x228: mtsprg1({{SPRG1 = Rs;}}); - 0x248: mtsprg2({{SPRG2 = Rs;}}); - 0x268: mtsprg3({{SPRG3 = Rs;}}); + 0x390: mttbl({{ TBL = Rs; }}); + 0x3a0: mtamr({{AMR = Rs;}}, [ IsPrivileged ]); + 0x3a1: mtiamr({{IAMR = Rs;}}); + 0x3a4: mtuamor({{UAMOR = Rs;}}, [ IsPrivileged ]); + 0x3aa: mtamor({{AMOR = Rs;}}); + 0x3c5: mthfscr({{HFSCR = Rs;}}); + 0x3c8: mttbu40({{TBU40 = Rs;}}); 0x3c9: mtlpcr({{LPCR = Rs;}}); - 0x324: mtfscr({{FSCR = Rs;}}); - 0x258: mtmmcra({{MMCRA = Rs;}}); - 0x378: mtmmcr0({{MMCR0 = Rs;}}); 0x3d8: mtmmcr1({{MMCR1 = Rs;}}); - 0x238: mtmmcr2({{MMCR2 = Rs;}}); - 0x2fa: mtpsscr({{PSSCR = Rs;}}); 0x3e9: mtlpidr({{LPIDR = Rs;}}); - 0x201: mtpidr({{PIDR = Rs;}}); - 0x3c5: mthfscr({{HFSCR = Rs;}}); - 0x27a: mtmmcrc({{MMCRC = Rs;}}); - 0x209: mthsprg0({{HSPRG0 = Rs;}}); - 0x21f: mthir0({{HIR0 = Rs;}}); - 0x3aa: mtamor({{AMOR = Rs;}}); - 0x3a1: mtiamr({{IAMR = Rs;}}); - 0x369: mthssr1({{HSRR1 = Rs;}}); - 0x349: mthssr0({{HSRR0 = Rs;}}); - 0x2c9: mthdec({{HDEC = Rs;}}); - 0x24a: mtpcr({{PCR = Rs;}}); } 83: mfmsr({{ Rt = MSR; }}, [ IsPrivileged ]); diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 550689804..7f2a9da8f 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -107,6 +107,44 @@ def operands {{ 'HSRR0': ('IntReg', 'ud', 'INTREG_HSRR0', 'IsInteger' , 9), 'HDEC': ('IntReg', 'ud', 'INTREG_HDEC', 'IsInteger' , 9), 'PCR': ('IntReg', 'ud', 'INTREG_PCR', 'IsInteger' , 9), + 'AMR': ('IntReg', 'ud', 'INTREG_AMR', 'IsInteger' , 9), + 'TFHAR': ('IntReg', 'ud', 'INTREG_TFHAR', 'IsInteger' , 9), + 'TFIAR': ('IntReg', 'ud', 'INTREG_TFIAR', 'IsInteger' , 9), + 'TEXASR': ('IntReg', 'ud', 'INTREG_TEXASR', 'IsInteger' , 9), + 'TIDR': ('IntReg', 'ud', 'INTREG_TIDR', 'IsInteger' , 9), + 'UAMOR': ('IntReg', 'ud', 'INTREG_UAMOR', 'IsInteger' , 9), + 'DPDES': ('IntReg', 'ud', 'INTREG_DPDES', 'IsInteger' , 9), + 'DAWR0': ('IntReg', 'ud', 'INTREG_DAWR0', 'IsInteger' , 9), + 'RPR': ('IntReg', 'ud', 'INTREG_RPR', 'IsInteger' , 9), + 'CIABR': ('IntReg', 'ud', 'INTREG_CIABR', 'IsInteger' , 9), + 'CIR': ('IntReg', 'uw', 'INTREG_CIR', 'IsInteger' , 9), + 'TBU40': ('IntReg', 'ud', 'INTREG_TBU40', 'IsInteger' , 9), + 'SPURR': ('IntReg', 'ud', 'INTREG_SPURR', 'IsInteger' , 9), + 'PURR': ('IntReg', 'ud', 'INTREG_PURR', 'IsInteger' , 9), + 'HDSISR': ('IntReg', 'uw', 'INTREG_HDSISR', 'IsInteger' , 9), + 'HDAR': ('IntReg', 'ud', 'INTREG_HDAR', 'IsInteger' , 9), + 'HRMOR': ('IntReg', 'ud', 'INTREG_HRMOR', 'IsInteger' , 9), + 'HMER': ('IntReg', 'ud', 'INTREG_HMER', 'IsInteger' , 9), + 'HMEER': ('IntReg', 'ud', 'INTREG_HMEER', 'IsInteger' , 9), + 'SIER': ('IntReg', 'ud', 'INTREG_SIER', 'IsInteger' , 9), + 'PMC1': ('IntReg', 'uw', 'INTREG_PMC1', 'IsInteger' , 9), + 'PMC2': ('IntReg', 'uw', 'INTREG_PMC2', 'IsInteger' , 9), + 'PMC3': ('IntReg', 'uw', 'INTREG_PMC3', 'IsInteger' , 9), + 'PMC4': ('IntReg', 'uw', 'INTREG_PMC4', 'IsInteger' , 9), + 'PMC5': ('IntReg', 'uw', 'INTREG_PMC5', 'IsInteger' , 9), + 'PMC6': ('IntReg', 'uw', 'INTREG_PMC6', 'IsInteger' , 9), + 'SDAR': ('IntReg', 'ud', 'INTREG_SDAR', 'IsInteger' , 9), + 'BESCRS': ('IntReg', 'ud', 'INTREG_BESCRS', 'IsInteger' , 9), + 'BESCRSU': ('IntReg', 'uw', 'INTREG_BESCRSU', 'IsInteger' , 9), + 'BESCRR': ('IntReg', 'ud', 'INTREG_BESCRR', 'IsInteger' , 9), + 'BESCRRU': ('IntReg', 'uw', 'INTREG_BESCRRU', 'IsInteger' , 9), + 'EBBHR': ('IntReg', 'ud', 'INTREG_EBBHR', 'IsInteger' , 9), + 'EBBRR': ('IntReg', 'ud', 'INTREG_EBBRR', 'IsInteger' , 9), + 'BESCR': ('IntReg', 'ud', 'INTREG_BESCR', 'IsInteger' , 9), + 'ASDR': ('IntReg', 'ud', 'INTREG_ASDR', 'IsInteger' , 9), + 'IC': ('IntReg', 'ud', 'INTREG_IC', 'IsInteger' , 9), + 'VTB': ('IntReg', 'ud', 'INTREG_VTB', 'IsInteger' , 9), + 'HSPRG1': ('IntReg', 'ud', 'INTREG_HSPRG1', 'IsInteger' , 9), # Setting as IntReg so things are stored as an integer, not double 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index e468ce3b6..3690fb641 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -64,7 +64,7 @@ const int NumIntArchRegs = 32; // CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR // and zero register, which doesn't actually exist but needs a number -const int NumIntSpecialRegs = 49; +const int NumIntSpecialRegs = 87; const int NumFloatArchRegs = 32; const int NumFloatSpecialRegs = 0; const int NumInternalProcRegs = 0; @@ -144,7 +144,45 @@ enum MiscIntRegNums { INTREG_HSRR0, INTREG_HSRR1, INTREG_HDEC, - INTREG_PCR + INTREG_PCR, + INTREG_AMR, + INTREG_TFHAR, + INTREG_TFIAR, + INTREG_TEXASR, + INTREG_TIDR, + INTREG_UAMOR, + INTREG_DPDES, + INTREG_DAWR0, + INTREG_RPR, + INTREG_CIABR, + INTREG_CIR, + INTREG_TBU40, + INTREG_SPURR, + INTREG_PURR, + INTREG_HDSISR, + INTREG_HDAR, + INTREG_HRMOR, + INTREG_HMER, + INTREG_HMEER, + INTREG_SIER, + INTREG_PMC1, + INTREG_PMC2, + INTREG_PMC3, + INTREG_PMC4, + INTREG_PMC5, + INTREG_PMC6, + INTREG_SDAR, + INTREG_BESCRS, + INTREG_BESCRSU, + INTREG_BESCRR, + INTREG_BESCRRU, + INTREG_EBBHR, + INTREG_EBBRR, + INTREG_BESCR, + INTREG_ASDR, + INTREG_IC, + INTREG_VTB, + INTREG_HSPRG1 }; } // namespace PowerISA -- 2.30.2