From 7f9d2d18251c3bec667993c744b568bbbe1a75ce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 09:15:30 -0700 Subject: [PATCH] Update CHANGELOG with "synth -abc9" --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 139f71672..44e32c6a8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" -- 2.30.2