From 7f9fbc9e73e0786aae516cbe8ccea15913846315 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 Apr 2022 14:05:37 +0100 Subject: [PATCH] list of hyperrams not just one --- src/ls2.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 283eb41..993186f 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -795,8 +795,8 @@ class DDR3SoC(SoC, Elaboratable): # and at the moment that's just UART tx/rx. ports = [] ports += [self.uart.tx_o, self.uart.rx_i] - if hasattr(self, "hyperram"): - ports += list(self.hyperram.ports()) + for hr in self.hyperramL + ports += list(hr.ports()) if hasattr(self, "ddrphy"): if hasattr(self.ddrphy, "pads"): # real PHY ports += list(self.ddrphy.pads.fields.values()) -- 2.30.2