From 7faf690912a0234f796dc39b5121b67efc30e6de Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 12 Mar 2020 20:28:41 +0000 Subject: [PATCH] vendor: fix a few issues in commit 2f8669ca. --- nmigen/lib/cdc.py | 3 ++- nmigen/vendor/intel.py | 2 +- nmigen/vendor/xilinx_7series.py | 2 +- nmigen/vendor/xilinx_spartan_3_6.py | 2 +- nmigen/vendor/xilinx_ultrascale.py | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py index 5c680cd..09cdd95 100644 --- a/nmigen/lib/cdc.py +++ b/nmigen/lib/cdc.py @@ -127,7 +127,8 @@ class AsyncFFSynchronizer(Elaboratable): self._stages = stages if async_edge not in ("pos", "neg"): - raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not {!r}" + raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', " + "not {!r}" .format(async_edge)) self._edge = async_edge diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py index 35f94ad..2f0c81f 100644 --- a/nmigen/vendor/intel.py +++ b/nmigen/vendor/intel.py @@ -403,7 +403,7 @@ class IntelPlatform(TemplatedPlatform): def get_async_ff_sync(self, async_ff_sync): m = Module() sync_output = Signal() - if async_ff_sync.edge == "pos": + if async_ff_sync._edge == "pos": m.submodules += Instance("altera_std_synchronizer", p_depth=async_ff_sync._stages, i_clk=ClockSignal(async_ff_sync._domain), diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index 37ebdcf..25bfa28 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -420,7 +420,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): for i, o in zip((0, *flops), flops): m.d.async_ff += o.eq(i) - if self._edge == "pos": + if async_ff_sync._edge == "pos": m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) else: m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py index 9fd9b33..c7d37d1 100644 --- a/nmigen/vendor/xilinx_spartan_3_6.py +++ b/nmigen/vendor/xilinx_spartan_3_6.py @@ -451,7 +451,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): for i, o in zip((0, *flops), flops): m.d.async_ff += o.eq(i) - if self._edge == "pos": + if async_ff_sync._edge == "pos": m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) else: m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py index 671b7c9..6598f0a 100644 --- a/nmigen/vendor/xilinx_ultrascale.py +++ b/nmigen/vendor/xilinx_ultrascale.py @@ -416,7 +416,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform): for i, o in zip((0, *flops), flops): m.d.async_ff += o.eq(i) - if self._edge == "pos": + if async_ff_sync._edge == "pos": m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) else: m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) -- 2.30.2